RISC-V: Add Types to Un-Typed Zicond Instructions

Creates a new "zicond" type and updates all zicond instructions
with that type.

gcc/ChangeLog:

	* config/riscv/riscv.md: Add "zicond" type
	* config/riscv/zicond.md: Update types

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index a6046c17fc3179a85e93a36ac5135ad18d882ca0..01cf623c0482c2bc401e3bce54dd3d73e21a03ac 100644 (file)
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -318,6 +318,7 @@
 ;; crypto cryptography instructions
 ;; pushpop    zc push and pop instructions
 ;; mvpair    zc move pair instructions
+;; zicond    zicond instructions
 ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
 ;; rdvlenb     vector byte length vlenb csrr read
 ;; rdvl        vector length vl csrr read
@@ -427,7 +428,7 @@
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
    rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
-   atomic,condmove,cbo,crypto,pushpop,mvpair,rdvlenb,rdvl,wrvxrm,wrfrm,
+   atomic,condmove,cbo,crypto,pushpop,mvpair,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,
    rdfrm,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,

diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 6627be3fa5856607b633b3ce36ccf6821a31ec10..05e7348abba1228f760843e613a2271cae06efb2 100644 (file)
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -40,7 +40,7 @@
     else
       gcc_unreachable ();
   }
-)
+[(set_attr "type" "zicond")])
 
 (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
   [(set (match_operand:GPR 0 "register_operand"                     "=r")
@@ -57,7 +57,7 @@
     else
       gcc_unreachable ();
   }
-)
+[(set_attr "type" "zicond")])
 
 ;; Special optimization under eq/ne in primitive semantics
 (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
@@ -75,7 +75,7 @@
     else
       gcc_unreachable ();
   }
-)
+[(set_attr "type" "zicond")])
 
 (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
   [(set (match_operand:GPR 0 "register_operand"                   "=r")
@@ -92,7 +92,7 @@
     else
       gcc_unreachable ();
   }
-)
+[(set_attr "type" "zicond")])
 
 ;; Combine creates this form in some cases (particularly the coremark
 ;; CRC loop).