//! Falcon microprocessor base support
use core::ops::Deref;
-use core::time::Duration;
use hal::FalconHal;
use kernel::bindings;
use kernel::device;
use kernel::prelude::*;
+use kernel::time::Delta;
use kernel::types::ARef;
use crate::dma::DmaObject;
/// Wait for memory scrubbing to complete.
fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result {
// TIMEOUT: memory scrubbing should complete in less than 20ms.
- util::wait_on(Duration::from_millis(20), || {
+ util::wait_on(Delta::from_millis(20), || {
if regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE).mem_scrubbing_done() {
Some(())
} else {
// According to OpenRM's `kflcnPreResetWait_GA102` documentation, HW sometimes does not set
// RESET_READY so a non-failing timeout is used.
- let _ = util::wait_on(Duration::from_micros(150), || {
+ let _ = util::wait_on(Delta::from_micros(150), || {
let r = regs::NV_PFALCON_FALCON_HWCFG2::read(bar, E::BASE);
if r.reset_ready() {
Some(())
// TODO[DLAY]: replace with udelay() or equivalent once available.
// TIMEOUT: falcon engine should not take more than 10us to reset.
- let _: Result = util::wait_on(Duration::from_micros(10), || None);
+ let _: Result = util::wait_on(Delta::from_micros(10), || None);
regs::NV_PFALCON_FALCON_ENGINE::alter(bar, E::BASE, |v| v.set_reset(false));
// Wait for the transfer to complete.
// TIMEOUT: arbitrarily large value, no DMA transfer to the falcon's small memories
// should ever take that long.
- util::wait_on(Duration::from_secs(2), || {
+ util::wait_on(Delta::from_secs(2), || {
let r = regs::NV_PFALCON_FALCON_DMATRFCMD::read(bar, E::BASE);
if r.idle() {
Some(())
}
// TIMEOUT: arbitrarily large value, firmwares should complete in less than 2 seconds.
- util::wait_on(Duration::from_secs(2), || {
+ util::wait_on(Delta::from_secs(2), || {
let r = regs::NV_PFALCON_FALCON_CPUCTL::read(bar, E::BASE);
if r.halted() {
Some(())
// SPDX-License-Identifier: GPL-2.0
use core::marker::PhantomData;
-use core::time::Duration;
use kernel::device;
use kernel::prelude::*;
+use kernel::time::Delta;
use crate::driver::Bar0;
use crate::falcon::{
.write(bar, E::BASE);
// TIMEOUT: falcon core should take less than 10ms to report being enabled.
- util::wait_on(Duration::from_millis(10), || {
+ util::wait_on(Delta::from_millis(10), || {
let r = regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE);
if r.valid() {
Some(())
//! the GPU is considered unusable until this step is completed, so we must wait on it before
//! performing driver initialization.
-use core::time::Duration;
-
use kernel::bindings;
use kernel::prelude::*;
+use kernel::time::Delta;
use crate::driver::Bar0;
use crate::regs;
pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result {
// TIMEOUT: arbitrarily large value. GFW starts running immediately after the GPU is put out of
// reset, and should complete in less time than that.
- util::wait_on(Duration::from_secs(4), || {
+ util::wait_on(Delta::from_secs(4), || {
// Check that FWSEC has lowered its protection level before reading the GFW_BOOT
// status.
let gfw_booted = regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK::read(bar)
// SPDX-License-Identifier: GPL-2.0
-use core::time::Duration;
-
use kernel::prelude::*;
-use kernel::time::Instant;
+use kernel::time::{Delta, Instant};
pub(crate) const fn to_lowercase_bytes<const N: usize>(s: &str) -> [u8; N] {
let src = s.as_bytes();
///
/// TODO[DLAY]: replace with `read_poll_timeout` once it is available.
/// (https://lore.kernel.org/lkml/20250220070611.214262-8-fujita.tomonori@gmail.com/)
-pub(crate) fn wait_on<R, F: Fn() -> Option<R>>(timeout: Duration, cond: F) -> Result<R> {
+pub(crate) fn wait_on<R, F: Fn() -> Option<R>>(timeout: Delta, cond: F) -> Result<R> {
let start_time = Instant::now();
loop {
return Ok(ret);
}
- if start_time.elapsed().as_nanos() > timeout.as_nanos() as i64 {
+ if start_time.elapsed().as_nanos() > timeout.as_nanos() {
return Err(ETIMEDOUT);
}
}