RISC-V: Add test for vec_duplicate + vnmsub.vv unsigned combine with GR2VR cost 0...

Add asm dump check and run test for vec_duplicate + vnmsub.vvm
combine to vnmsub.vx, with the GR2VR cost is 0, 2 and 15.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
	for vnmsub.vx.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c: New test.
	* gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index b9065ad880ce8af41edb37d67e177b899ce471f8..d191097e2bb38e255910d6877b126082ba5acb44 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index a4d422e2cdd61c71dbad55354c51923aa9d4ace5..e0b4b732c79c654b0583657b32e37568dab63fc9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 7d7ec75c8ea6abb89e9e14bdaf66952786cd75fb..65528400b5b494c58491600c9a67341551e1fbdb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -28,3 +28,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index 0cdda99b565bfb275a3c664c60a65772b56a2953..b659f7fbc0682a59c0fe13916910dd5bc592d88a 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-times {vmacc.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vnmsac.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vmadd.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vnmsub.vx} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index f460ccb88650d94cc69fe3ef9fde09113352b866..23479d97b650a0b786478c69f2a8f477ac126029 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 4ed60f5204cbbb0ed4d8e9ebaedb468362f40297..8c41bd85686b7df6c4f45b38fdb9e910718a8a28 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 2a7e3322f9a8c935855ae878df865b166bd179b2..abe16cd7b50961e73789a652433195b40fa972ab 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 923b9c34470e90c3aa4772bf0191c5bcc80ff7c2..957fcde118fad91ca8af6cfdb0a6d1c1f42bf876 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 3ddd6b19d681caee245f1900549d1489695e3c3e..f232d6a97bd721927bedc4a29cb83da5b184f525 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 609bdec6eff4f660b452465b185a3c56123eb074..24e187ce2b05f3e37634d75b7a1b09f48fd253d0 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index a498e53c8e5ad3bbe65a4dc4bfb7dac510871075..977aa463232e604f32d34e097bb2e170c1bee5c9 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index b9b624e1524c05119b4f9e8d19ea1a0aa3c83053..9deb635d0b9c8dff0e1b0ad2bad82677fbb44d6d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -25,3 +25,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T)
 /* { dg-final { scan-assembler-not {vmacc.vx} } } */
 /* { dg-final { scan-assembler-not {vnmsac.vx} } } */
 /* { dg-final { scan-assembler-not {vmadd.vx} } } */
+/* { dg-final { scan-assembler-not {vnmsub.vx} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c
new file mode 100644 (file)
index 0000000..95a771d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u16.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint16_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c
new file mode 100644 (file)
index 0000000..c013cf9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint32_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c
new file mode 100644 (file)
index 0000000..5f62dff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint64_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c
new file mode 100644 (file)
index 0000000..4508089
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vnmsub-run-1-u8.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_ternary.h"
+#include "vx_ternary_data.h"
+
+#define T          uint8_t
+#define NAME       nmsub
+#define TEST_DATA  TEST_TERNARY_DATA_WRAP(T, NAME)
+
+DEF_VX_TERNARY_CASE_1_WRAP(T, *, -, NAME)
+
+#define TEST_RUN(T, NAME, vd, vs2, rs1, n) \
+  RUN_VX_TERNARY_CASE_1_WRAP(T, NAME, vd, vs2, rs1, n)
+
+#include "vx_ternary_run.h"