arm64: dts: renesas: r9a08g045: Add PCIe node

The RZ/G3S SoC has a variant (R9A08G045S33) which supports PCIe. Add the
PCIe node.

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20251119143523.977085-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 876de634908ef63a93a8e8d887e50ac240e9fe8f..997e6cf0bb824659809ff3d724fb31812ad94ac4 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -845,6 +845,71 @@
                        status = "disabled";
                };
 
+               pcie: pcie@11e40000 {
+                       compatible = "renesas,r9a08g045-pcie";
+                       reg = <0 0x11e40000 0 0x10000>;
+                       ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>;
+                       /* Map all possible DRAM ranges (4 GB). */
+                       dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>;
+                       bus-range = <0x0 0xff>;
+                       interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "serr", "serr_cor", "serr_nonfatal",
+                                         "serr_fatal", "axi_err", "inta",
+                                         "intb", "intc", "intd", "msi",
+                                         "link_bandwidth", "pm_pme", "dma",
+                                         "pcie_evt", "msg", "all";
+                       #interrupt-cells = <1>;
+                       interrupt-controller;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
+                                       <0 0 0 2 &pcie 0 0 0 1>, /* INTB */
+                                       <0 0 0 3 &pcie 0 0 0 2>, /* INTC */
+                                       <0 0 0 4 &pcie 0 0 0 3>; /* INTD */
+                       clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,
+                                <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;
+                       clock-names = "aclk", "pm";
+                       resets = <&cpg R9A08G045_PCI_ARESETN>,
+                                <&cpg R9A08G045_PCI_RST_B>,
+                                <&cpg R9A08G045_PCI_RST_GP_B>,
+                                <&cpg R9A08G045_PCI_RST_PS_B>,
+                                <&cpg R9A08G045_PCI_RST_RSM_B>,
+                                <&cpg R9A08G045_PCI_RST_CFG_B>,
+                                <&cpg R9A08G045_PCI_RST_LOAD_B>;
+                       reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",
+                                     "rst_rsm_b", "rst_cfg_b", "rst_load_b";
+                       power-domains = <&cpg>;
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       renesas,sysc = <&sysc>;
+                       status = "disabled";
+
+                       pcie_port0: pcie@0,0 {
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               ranges;
+                               device_type = "pci";
+                               vendor-id = <0x1912>;
+                               device-id = <0x0033>;
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                       };
+               };
+
                gic: interrupt-controller@12400000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <3>;