]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
KVM: SVM: Fold svm_vcpu_init_msrpm() into its sole caller
authorSean Christopherson <seanjc@google.com>
Tue, 10 Jun 2025 22:57:27 +0000 (15:57 -0700)
committerSean Christopherson <seanjc@google.com>
Fri, 20 Jun 2025 20:07:31 +0000 (13:07 -0700)
Fold svm_vcpu_init_msrpm() into svm_recalc_msr_intercepts() now that there
is only the one caller (and because the "init" misnomer is even more
misleading than it was in the past).

No functional change intended.

Link: https://lore.kernel.org/r/20250610225737.156318-23-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
arch/x86/kvm/svm/svm.c

index dd5da5e4f844b94b22ef62aee066297bb6dbb596..c17eeeea8e643744e6bd6afaaf3519c61124952d 100644 (file)
@@ -773,21 +773,6 @@ static void svm_recalc_lbr_msr_intercepts(struct kvm_vcpu *vcpu)
                svm_set_intercept_for_msr(vcpu, MSR_IA32_DEBUGCTLMSR, MSR_TYPE_RW, intercept);
 }
 
-static void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu)
-{
-       svm_disable_intercept_for_msr(vcpu, MSR_STAR, MSR_TYPE_RW);
-       svm_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
-
-#ifdef CONFIG_X86_64
-       svm_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
-       svm_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
-       svm_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
-       svm_disable_intercept_for_msr(vcpu, MSR_LSTAR, MSR_TYPE_RW);
-       svm_disable_intercept_for_msr(vcpu, MSR_CSTAR, MSR_TYPE_RW);
-       svm_disable_intercept_for_msr(vcpu, MSR_SYSCALL_MASK, MSR_TYPE_RW);
-#endif
-}
-
 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept)
 {
        static const u32 x2avic_passthrough_msrs[] = {
@@ -846,7 +831,17 @@ static void svm_recalc_msr_intercepts(struct kvm_vcpu *vcpu)
 {
        struct vcpu_svm *svm = to_svm(vcpu);
 
-       svm_vcpu_init_msrpm(vcpu);
+       svm_disable_intercept_for_msr(vcpu, MSR_STAR, MSR_TYPE_RW);
+       svm_disable_intercept_for_msr(vcpu, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
+
+#ifdef CONFIG_X86_64
+       svm_disable_intercept_for_msr(vcpu, MSR_GS_BASE, MSR_TYPE_RW);
+       svm_disable_intercept_for_msr(vcpu, MSR_FS_BASE, MSR_TYPE_RW);
+       svm_disable_intercept_for_msr(vcpu, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
+       svm_disable_intercept_for_msr(vcpu, MSR_LSTAR, MSR_TYPE_RW);
+       svm_disable_intercept_for_msr(vcpu, MSR_CSTAR, MSR_TYPE_RW);
+       svm_disable_intercept_for_msr(vcpu, MSR_SYSCALL_MASK, MSR_TYPE_RW);
+#endif
 
        if (lbrv)
                svm_recalc_lbr_msr_intercepts(vcpu);