drm/msm/a6xx: Set GMU CGC properties on a6xx too

This was apparently never done before.. Program the expected values.

This also gets rid of sneakily setting that register through the HWCG
reg list on A690.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/611098/
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 646da85a16feb00f0961289984d0953552106f52..3f7f9b035e26c8c8ee6ad773d192a77bf7ea8da7 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -448,7 +448,6 @@ static const struct adreno_reglist a690_hwcg[] = {
        {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
        {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
        {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
-       {REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, 0x20200},
        {REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, 0x10111},
        {REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, 0x5555},
        {}

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 69e09be623bfee02bed9f61c94af2b6418f3bfc9..41c5b33e2e3799515ba880da693f12f58df97adc 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -402,6 +402,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
        struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
        const struct adreno_reglist *reg;
        unsigned int i;
+       u32 cgc_delay, cgc_hyst;
        u32 val, clock_cntl_on;
 
        if (!(adreno_gpu->info->a6xx->hwcg || adreno_is_a7xx(adreno_gpu)))
@@ -416,14 +417,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
        else
                clock_cntl_on = 0x8aa8aa82;
 
-       if (adreno_is_a7xx(adreno_gpu)) {
-               gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
-                         state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
-               gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
-                         state ? 0x10111 : 0);
-               gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
-                         state ? 0x5555 : 0);
-       }
+       cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
+       cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
+
+       gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
+                       state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
+       gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL,
+                       state ? cgc_delay : 0);
+       gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL,
+                       state ? cgc_hyst : 0);
 
        if (!adreno_gpu->info->a6xx->hwcg) {
                gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1);

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index db42f8af978d6d00d66c4de66677041220645458..6f604da23259d10c40db99bb7b1628311517e3ec 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -463,7 +463,13 @@ static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
        return adreno_is_a610(gpu) || adreno_is_a702(gpu);
 }
 
-/* check for a615, a616, a618, a619 or any a630 derivatives */
+/* TODO: 615/616 */
+static inline int adreno_is_a615_family(const struct adreno_gpu *gpu)
+{
+       return adreno_is_a618(gpu) ||
+              adreno_is_a619(gpu);
+}
+
 static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)
 {
        if (WARN_ON_ONCE(!gpu->info))