PCI: Wait for device readiness after D3hot -> D0uninitialized transition

For a device that advertises No_Soft_Reset == 0, a transition from D3hot to
D0uninitialized is a soft reset, and the resulting internal device state is
undefined.

Per PCIe r7.0, sec 2.3.1, a transition from D3hot to D0uninitialized
mandates a minimum 10 ms delay before accessing the device. Following this
delay, the device is permitted to respond to initial configuration requests
with a Request Retry Status (RRS) completion status if it needs more time
to initialize.

Call pci_dev_wait() after pci_power_up() performs a D3hot->D0uninitialized
transition to ensure the device is ready to accept config accesses, as is
done after the similar transition in pci_pm_reset().

If the device is already ready, this is essentially a no-op except for one
additional config read.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki (Intel) <rafael@kernel.org>
Link: https://patch.msgid.link/20260518191220.636213-3-bhelgaas@google.com

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 5a9af0bb2c71cfbf37ac8469968a4851b55c2f60..8228d2782f9590c62aafe1b0f95f7bb728b8982b 100644 (file)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -1300,7 +1300,18 @@ int pci_power_up(struct pci_dev *dev)
        bool need_restore;
        pci_power_t state;
        u16 pmcsr;
+       int ret;
 
+       /*
+        * When setting power state to D0, platform_pci_set_power_state()
+        * ensures main power is on.  If it puts the device in D0, it also
+        * completes any required delays after the transition; if it leaves
+        * the device in D1, D2, or D3hot, we use the PM Capability to
+        * transition to D0.
+        *
+        * In all cases, the device is either Configuration-Ready or
+        * inaccessible upon return.
+        */
        platform_pci_set_power_state(dev, PCI_D0);
 
        if (!dev->pm_cap) {
@@ -1341,10 +1352,19 @@ int pci_power_up(struct pci_dev *dev)
        pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
 
        /* Mandatory transition delays; see PCI PM 1.2. */
-       if (state == PCI_D3hot)
+       if (state == PCI_D3hot) {
                pci_dev_d3_sleep(dev);
-       else if (state == PCI_D2)
+               if (!(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET)) {
+                       ret = pci_dev_wait(dev, "power up D3hot->D0uninitialized",
+                                          PCIE_RESET_READY_POLL_MS);
+                       if (ret) {
+                               dev->current_state = PCI_D3cold;
+                               return -EIO;
+                       }
+               }
+       } else if (state == PCI_D2) {
                udelay(PCI_PM_D2_DELAY);
+       }
 
 end:
        dev->current_state = PCI_D0;