arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes

[ Upstream commit 833948fb2b63155847ab691a54800f801555429b ]

The RZ/G2L(C) SoC is equipped with the GIC-600. The GICD is 64KiB +
64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per
CPU.

Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/20240730122436.350013-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 5f3bc2898daf2d92bb3d81897ff3094bd636ca47..0818560913028e14959bbf457a6a3f39fd93b36c 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -300,8 +300,8 @@
                        #interrupt-cells = <3>;
                        #address-cells = <0>;
                        interrupt-controller;
-                       reg = <0x0 0x11900000 0 0x40000>,
-                             <0x0 0x11940000 0 0x60000>;
+                       reg = <0x0 0x11900000 0 0x20000>,
+                             <0x0 0x11940000 0 0x40000>;
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
                };
        };