Fix error in 64-bit and smaller load versions of

LDR/STR (immediate, SIMD&FP, unsigned offset)

git-svn-id: svn://svn.valgrind.org/vex/trunk@2831

diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index b8a5875bb1809781977837319a84b5e20bfcd262..73c7f8bb169d471cb0f61df371b15562de5f4315 100644 (file)
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -3276,7 +3276,6 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn)
                     getIReg64orZR(rT2));
          } else {
             vassert(bL == 0 && bX == 0);
-            vassert(0); //ATC
             // 32 bit store
             storeLE(binop(Iop_Add64,mkexpr(tTA),mkU64(0)),
                     getIReg32orZR(rT1));
@@ -3685,8 +3684,14 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn)
          }
 
          if (isLD) {
+            if (szB < 16) {
+               putQReg128(tt1, mkV128(0x0000));
+            }
             putQRegLO(tt1,
                       loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(0))));
+            if (szB < 16) {
+               putQReg128(tt2, mkV128(0x0000));
+            }
             putQRegLO(tt2,
                       loadLE(ty, binop(Iop_Add64, mkexpr(tTA), mkU64(szB))));
          } else {