rs6000: Don't allow AltiVec address in movoo & movxo pattern [PR110411]

There are no instructions that do traditional AltiVec addresses (i.e.
with the low four bits of the address masked off) for OOmode and XOmode
objects. The solution is to modify the constraints used in the movoo and
movxo pattern to disallow these types of addresses, which assists LRA in
resolving this issue. Furthermore, the mode size 16 check has been
removed in vsx_quad_dform_memory_operand to allow OOmode and XOmode, and
quad_address_p already handles less than size 16.

2023-08-31  Jeevitha Palanisamy  <jeevitha@linux.ibm.com>

gcc/
	PR target/110411
	* config/rs6000/mma.md (define_insn_and_split movoo): Disallow
	AltiVec address operands.
	(define_insn_and_split movxo): Likewise.
	* config/rs6000/predicates.md (vsx_quad_dform_memory_operand): Remove
	redundant mode size check.

gcc/testsuite/
	PR target/110411
	* gcc.target/powerpc/pr110411-1.c: New testcase.
	* gcc.target/powerpc/pr110411-2.c: New testcase.

(cherry picked from commit 9ea1248604d7b65009af32103814332f35bd33e2)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 2bf4d1718e39374b98d7cdfb08c3c33d4fbb494b..b25d5a997abdc6d24c15128d37d705cc8ca0eb9b 100644 (file)
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -292,8 +292,8 @@
 })
 
 (define_insn_and_split "*movoo"
-  [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,m,wa")
-       (match_operand:OO 1 "input_operand" "m,wa,wa"))]
+  [(set (match_operand:OO 0 "nonimmediate_operand" "=wa,ZwO,wa")
+       (match_operand:OO 1 "input_operand" "ZwO,wa,wa"))]
   "TARGET_MMA
    && (gpc_reg_operand (operands[0], OOmode)
        || gpc_reg_operand (operands[1], OOmode))"
@@ -339,8 +339,8 @@
 })
 
 (define_insn_and_split "*movxo"
-  [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,d")
-       (match_operand:XO 1 "input_operand" "m,d,d"))]
+  [(set (match_operand:XO 0 "nonimmediate_operand" "=d,ZwO,d")
+       (match_operand:XO 1 "input_operand" "ZwO,d,d"))]
   "TARGET_MMA
    && (gpc_reg_operand (operands[0], XOmode)
        || gpc_reg_operand (operands[1], XOmode))"

diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index edc8cab0e0eb1cf8e232dea125f9d69028ab2ea3..5a8b1236334de9b0122dc2fb860f6a87143f56f3 100644 (file)
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -780,7 +780,7 @@
 (define_predicate "vsx_quad_dform_memory_operand"
   (match_code "mem")
 {
-  if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
+  if (!TARGET_P9_VECTOR)
     return false;
 
   return quad_address_p (XEXP (op, 0), mode, false);

diff --git a/gcc/testsuite/gcc.target/powerpc/pr110411-1.c b/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
new file mode 100644 (file)
index 0000000..6b0dbb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110411-1.c
@@ -0,0 +1,21 @@
+/* PR target/110411 */
+/* { dg-options "-O2 -mdejagnu-cpu=power10 -mblock-ops-vector-pair" } */
+
+/* Verify we do not ICE on the following.  */
+
+#include <string.h>
+
+struct s {
+  long a;
+  long b;
+  long c;
+  long d: 1;
+};
+unsigned long ptr;
+
+void
+bug (struct s *dst)
+{
+  struct s *src = (struct s *)(ptr & ~0xFUL);
+  memcpy (dst, src, sizeof(struct s));
+}

diff --git a/gcc/testsuite/gcc.target/powerpc/pr110411-2.c b/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
new file mode 100644 (file)
index 0000000..c2046fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr110411-2.c
@@ -0,0 +1,12 @@
+/* PR target/110411 */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Verify we do not ICE on the following.  */
+
+void
+bug (__vector_quad *dst)
+{
+  dst = (__vector_quad *)((unsigned long)dst & ~0xFUL);
+  __builtin_mma_xxsetaccz (dst);
+}