RISC-V: Add test cases for vwsubu.vv reg overlap

Add test cases for register group overlap, please
note it is not overlap as much as possible.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m1.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf2.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf4.c: New test.
	* gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf8.c: New test.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com>

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m1.c
new file mode 100644 (file)
index 0000000..dd70724
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vuint16m1_t,
+  vuint32m2_t,
+  __riscv_vle16_v_u16m1,
+  __riscv_vwsubu_vv_u32m2,
+  __riscv_vse32_v_u32m2,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m2.c
new file mode 100644 (file)
index 0000000..6f4e8fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m2,
+  vuint16m2_t,
+  vuint32m4_t,
+  __riscv_vle16_v_u16m2,
+  __riscv_vwsubu_vv_u32m4,
+  __riscv_vse32_v_u32m4,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m4.c
new file mode 100644 (file)
index 0000000..23cc3f9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m4,
+  vuint16m4_t,
+  vuint32m8_t,
+  __riscv_vle16_v_u16m4,
+  __riscv_vwsubu_vv_u32m8,
+  __riscv_vse32_v_u32m8,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf2.c
new file mode 100644 (file)
index 0000000..9592d3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf2_t,
+  vuint32m1_t,
+  __riscv_vle16_v_u16mf2,
+  __riscv_vwsubu_vv_u32m1,
+  __riscv_vse32_v_u32m1,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf4.c
new file mode 100644 (file)
index 0000000..d14d29a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u16-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e16m1,
+  vuint16mf4_t,
+  vuint32mf2_t,
+  __riscv_vle16_v_u16mf4,
+  __riscv_vwsubu_vv_u32mf2,
+  __riscv_vse32_v_u32mf2,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m1.c
new file mode 100644 (file)
index 0000000..925db96
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m1,
+  vuint32m1_t,
+  vuint64m2_t,
+  __riscv_vle32_v_u32m1,
+  __riscv_vwsubu_vv_u64m2,
+  __riscv_vse64_v_u64m2,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m2.c
new file mode 100644 (file)
index 0000000..371dd34
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m2,
+  vuint32m2_t,
+  vuint64m4_t,
+  __riscv_vle32_v_u32m2,
+  __riscv_vwsubu_vv_u64m4,
+  __riscv_vse64_v_u64m4,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m4.c
new file mode 100644 (file)
index 0000000..471e348
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m4,
+  vuint32m4_t,
+  vuint64m8_t,
+  __riscv_vle32_v_u32m4,
+  __riscv_vwsubu_vv_u64m8,
+  __riscv_vse64_v_u64m8,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-mf2.c
new file mode 100644 (file)
index 0000000..08711ee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u32-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e32m1,
+  vuint32mf2_t,
+  vuint64m1_t,
+  __riscv_vle32_v_u32mf2,
+  __riscv_vwsubu_vv_u64m1,
+  __riscv_vse64_v_u64m1,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m1.c
new file mode 100644 (file)
index 0000000..bd0ee69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m1.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8m1_t,
+  vuint16m2_t,
+  __riscv_vle8_v_u8m1,
+  __riscv_vwsubu_vv_u16m2,
+  __riscv_vse16_v_u16m2,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v2,v1,v3([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v10,v11,v3([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m2.c
new file mode 100644 (file)
index 0000000..b258605
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m2.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m2,
+  vuint8m2_t,
+  vuint16m4_t,
+  __riscv_vle8_v_u8m2,
+  __riscv_vwsubu_vv_u16m4,
+  __riscv_vse16_v_u16m4,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X8)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v8,v10,v6([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v28,v30,v24([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m4.c
new file mode 100644 (file)
index 0000000..96cf083
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-m4.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m4,
+  vuint8m4_t,
+  vuint16m8_t,
+  __riscv_vle8_v_u8m4,
+  __riscv_vwsubu_vv_u16m8,
+  __riscv_vse16_v_u16m8,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X4)
+
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v8,v4,v12([^0-9]|$)} 1 } } */
+/* { dg-final { scan-assembler-times {vwsubu\.vv\s+v24,v28,v16([^0-9]|$)} 1 } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf2.c
new file mode 100644 (file)
index 0000000..8e2e4c2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf2.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf2_t,
+  vuint16m1_t,
+  __riscv_vle8_v_u8mf2,
+  __riscv_vwsubu_vv_u16m1,
+  __riscv_vse16_v_u16m1,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf4.c
new file mode 100644 (file)
index 0000000..7cedc3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf4.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf4_t,
+  vuint16mf2_t,
+  __riscv_vle8_v_u8mf4,
+  __riscv_vwsubu_vv_u16mf2,
+  __riscv_vse16_v_u16mf2,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf8.c
new file mode 100644 (file)
index 0000000..b42ae24
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/group_overlap/vwsubu_vv-u8-mf8.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
+
+#include "group_overlap.h"
+
+DEF_GROUP_OVERLAP_BINARY_1(
+  __riscv_vsetvlmax_e8m1,
+  vuint8mf8_t,
+  vuint16mf4_t,
+  __riscv_vle8_v_u8mf8,
+  __riscv_vwsubu_vv_u16mf4,
+  __riscv_vse16_v_u16mf4,
+  vwsubu_vv,
+  LOOP_DUAL_WIDEN_BINARY_BODY_X16)
+
+/* The fractional LMUL source has EMUL < 1, thus the widened destination
+   register group must not overlap either source at all.  */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),\1,} } } */
+/* { dg-final { scan-assembler-not {vwsubu\.vv\s+(v[0-9]+),v[0-9]+,\1([^0-9]|$)} } } */