arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.

PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
attaches while PCIe1 routes to a standard PCIe x4 expansion slot.
Hence, enable the PCIe0 and PCIe1 controller and phy-nodes.

Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@quicinc.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20251128104928.4070050-7-ziyue.zhang@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts
index 15cfb3aa3fa86345907aa3a70360d95117ae2914..565418b86b2ad9588d6200cd6765f9716d3e90df 100644 (file)
--- a/arch/arm64/boot/dts/qcom/monaco-evk.dts
+++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts
@@ -411,6 +411,44 @@
        status = "okay";
 };
 
+&pcie0 {
+       pinctrl-0 = <&pcie0_default_state>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie0_phy {
+       vdda-phy-supply = <&vreg_l6a>;
+       vdda-pll-supply = <&vreg_l5a>;
+
+       status = "okay";
+};
+
+&pcie1 {
+       pinctrl-0 = <&pcie1_default_state>;
+       pinctrl-names = "default";
+
+       status = "okay";
+};
+
+&pcie1_phy {
+       vdda-phy-supply = <&vreg_l6a>;
+       vdda-pll-supply = <&vreg_l5a>;
+
+       status = "okay";
+};
+
+&pcieport0 {
+       reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+};
+
+&pcieport1 {
+       reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+};
+
 &qupv3_id_0 {
        firmware-name = "qcom/qcs8300/qupv3fw.elf";
        status = "okay";
@@ -456,6 +494,30 @@
 };
 
 &tlmm {
+
+       pcie0_default_state: pcie0-default-state {
+               wake-pins {
+                       pins = "gpio0";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               clkreq-pins {
+                       pins = "gpio1";
+                       function = "pcie0_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-pins {
+                       pins = "gpio2";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
        ethernet0_default: ethernet0-default-state {
                ethernet0_mdc: ethernet0-mdc-pins {
                        pins = "gpio5";
@@ -479,6 +541,29 @@
                bias-pull-up;
        };
 
+       pcie1_default_state: pcie1-default-state {
+               wake-pins {
+                       pins = "gpio21";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               clkreq-pins {
+                       pins = "gpio22";
+                       function = "pcie1_clkreq";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+
+               perst-pins {
+                       pins = "gpio23";
+                       function = "gpio";
+                       drive-strength = <2>;
+                       bias-pull-up;
+               };
+       };
+
        qup_i2c15_default: qup-i2c15-state {
                pins = "gpio91", "gpio92";
                function = "qup1_se7";