]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
serial: sc16is7xx: add comments for lock requirements
authorHugo Villeneuve <hvilleneuve@dimonoff.com>
Mon, 27 Oct 2025 14:29:56 +0000 (10:29 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 28 Oct 2025 14:25:41 +0000 (15:25 +0100)
Indicate why lock needs to be asserted when accessing
MSR register, as this is not immediately obvious when looking at this
register in the device datasheet.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://patch.msgid.link/20251027142957.1032073-15-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/tty/serial/sc16is7xx.c

index 4898b4235d0dad44f53efd1a6a55af1917d66b4e..1fd64a47341d8263c82fcadd90a4c2e549193e19 100644 (file)
@@ -499,10 +499,10 @@ EXPORT_SYMBOL_GPL(sc16is762_devtype);
 static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
 {
        switch (reg) {
-       case SC16IS7XX_RHR_REG:
-       case SC16IS7XX_IIR_REG:
-       case SC16IS7XX_LSR_REG:
-       case SC16IS7XX_MSR_REG:
+       case SC16IS7XX_RHR_REG: /* Shared address space with THR & DLL */
+       case SC16IS7XX_IIR_REG: /* Shared address space with FCR & EFR */
+       case SC16IS7XX_LSR_REG: /* Shared address space with XON2 */
+       case SC16IS7XX_MSR_REG: /* Shared address space with TCR & XOFF1 */
        case SC16IS7XX_SPR_REG: /* Shared address space with TLR & XOFF2 */
        case SC16IS7XX_TXLVL_REG:
        case SC16IS7XX_RXLVL_REG:
@@ -711,6 +711,7 @@ static void sc16is7xx_update_mlines(struct sc16is7xx_one *one)
        unsigned long flags;
        unsigned int status, changed;
 
+       /* Lock required as MSR address is shared with TCR and XOFF1. */
        lockdep_assert_held_once(&one->lock);
 
        status = sc16is7xx_get_hwmctrl(port);