drm/msm: Add sysprof accessors

Currently the sysprof param serves two functions, (a) disabling perfcntr
clearing on context switch/preemption, and (b) disabling IFPC.  In the
future, with kernel side global perfcntr collection/stream, the decision
about disabling IFPC will change.

To prepare for this, split out two helpers/accessors for the two
different cases.  For now, they are the same thing, but this will
change.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Anna Maniscalco <anna.maniscalco2000@gmail.com>
Reviewed-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/728214/
Message-ID: <20260526145137.160554-8-robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 616198a836a4ddea17ecbd1fdd175e9c9c9656ec..d26f8733672dd9c07e8c78043c1da18a2511e1f7 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2080,10 +2080,10 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
 
 void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu)
 {
+       bool sysprof = msm_gpu_sysprof_no_ifpc(gpu);
        struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
        struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
        struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
-       unsigned int sysprof_active;
 
        /* Nothing to do if GPU is suspended. We will handle this during GMU resume */
        if (!pm_runtime_get_if_active(&gpu->pdev->dev))
@@ -2091,15 +2091,13 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu)
 
        mutex_lock(&gmu->lock);
 
-       sysprof_active = refcount_read(&gpu->sysprof_active);
-
        /*
         * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that,
         * use the currently unused perfcounter oob vote to block IFPC when sysprof is active
         */
-       if ((sysprof_active > 1) && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
+       if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
                a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
-       else if ((sysprof_active == 1) && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
+       else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
                a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
 
        mutex_unlock(&gmu->lock);

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index e9424d20277ce1a6179b4c06f04343c7c1c38ec4..d24601cb162d1b746c4885ae9a928b7cc1ed06e3 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -203,7 +203,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
                struct msm_ringbuffer *ring, struct msm_gem_submit *submit)
 {
-       bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
+       bool sysprof = msm_gpu_sysprof_no_perfcntr_zap(&a6xx_gpu->base.base);
        struct msm_context *ctx = submit->queue->ctx;
        struct drm_gpuvm *vm = msm_context_vm(submit->dev, ctx);
        struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
@@ -1531,7 +1531,7 @@ out:
                a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
        }
 
-       if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) {
+       if (!ret && msm_gpu_sysprof_no_ifpc(gpu)) {
                ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
                if (!ret)
                        set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status);
@@ -2776,6 +2776,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
                .create_private_vm = a6xx_create_private_vm,
                .get_rptr = a6xx_get_rptr,
                .progress = a8xx_progress,
+               .sysprof_setup = a6xx_gmu_sysprof_setup,
        },
        .init = a6xx_gpu_init,
        .get_timestamp = a8xx_gmu_get_timestamp,

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c
index df4cbf42e9a40fbe267a33f7463b5b7fc4116e25..1e599d4ddea1c867af54337dd3fb73538b0453a1 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c
@@ -261,7 +261,7 @@ void a6xx_preempt_trigger(struct msm_gpu *gpu)
        mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000));
 
        /* Enable or disable postamble as needed */
-       sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
+       sysprof = msm_gpu_sysprof_no_perfcntr_zap(gpu);
 
        if (!sysprof && !a6xx_gpu->postamble_enabled)
                preempt_prepare_postamble(a6xx_gpu);

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index 86f2b1af9e2a643d2e4ae6c0378b0b4e3de7d805..9cf307cf9fdadde9a1d70de7b52c39c9f2f07d02 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -845,7 +845,7 @@ out:
         */
        a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
 
-       if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) {
+       if (!ret && msm_gpu_sysprof_no_perfcntr_zap(gpu)) {
                ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
                if (!ret)
                        set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status);

diff --git a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c b/drivers/gpu/drm/msm/adreno/a8xx_preempt.c
index 3d8c33ba722e3c6b0574e1ac5f1d7a0ebb3c14fd..6cb53a0718018efcecbe0ab1b73a7b51a28b1dc5 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a8xx_preempt.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_preempt.c
@@ -242,7 +242,7 @@ void a8xx_preempt_trigger(struct msm_gpu *gpu)
        mod_timer(&a6xx_gpu->preempt_timer, jiffies + msecs_to_jiffies(10000));
 
        /* Enable or disable postamble as needed */
-       sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
+       sysprof = msm_gpu_sysprof_no_perfcntr_zap(gpu);
 
        if (!sysprof && !a6xx_gpu->postamble_enabled)
                preempt_prepare_postamble(a6xx_gpu);

diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 9b91d79dc277f7e07052b1b2f94b80aa1139f9e4..bdafdf20f3f761841bb9a475d1fcd842f365566b 100644 (file)
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -311,6 +311,24 @@ static inline bool msm_gpu_active(struct msm_gpu *gpu)
        return false;
 }
 
+static inline bool
+msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu)
+{
+       return refcount_read(&gpu->sysprof_active) > 1;
+}
+
+static inline bool
+msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu)
+{
+       /*
+        * For now, this is the same condition as disabling perfcntr clears
+        * on context switch.  But once kernel perfcntr IFPC support is in
+        * place, we will only need to disable IFPC for legacy userspace
+        * setting SYSPROF param.
+        */
+       return msm_gpu_sysprof_no_perfcntr_zap(gpu);
+}
+
 /*
  * The number of priority levels provided by drm gpu scheduler.  The
  * DRM_SCHED_PRIORITY_KERNEL priority level is treated specially in some