], description="L2 data cache analysis")
+def IntelMlp() -> Optional[Metric]:
+ try:
+ l1d = Event("L1D_PEND_MISS.PENDING")
+ l1dc = Event("L1D_PEND_MISS.PENDING_CYCLES")
+ except:
+ return None
+
+ l1dc = Select(l1dc / 2, Literal("#smt_on"), l1dc)
+ ml = d_ratio(l1d, l1dc)
+ return Metric("lpm_mlp",
+ "Miss level parallelism - number of outstanding load misses per cycle (higher is better)",
+ ml, "load_miss_pending/cycle")
+
+
def IntelPorts() -> Optional[MetricGroup]:
pipeline_events = json.load(
open(f"{_args.events_path}/x86/{_args.model}/pipeline.json"))
IntelIlp(),
IntelL2(),
IntelLdSt(),
+ IntelMlp(),
IntelPorts(),
IntelSwpf(),
])