RISC-V: Change truncate to float_truncate in narrowing patterns.

This fixes a bug in the autovect FP narrowing patterns which resulted in
a combine ICE.  It would try to e.g. simplify a unary operation by
simplify_const_unary_operation which obviously expects a float_truncate
and not a truncate for a floating-point mode.

gcc/ChangeLog:

	* config/riscv/autovec.md: Use float_truncate.

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 4ab0e9f99eba5db49d4eb78a4b062a084125ed47..0fc2bf5186fbda9cd230b052a21d2709645b1d9a 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -473,7 +473,7 @@
 ;; -------------------------------------------------------------------------
 (define_insn_and_split "trunc<mode><v_double_trunc>2"
   [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vr")
-    (truncate:<V_DOUBLE_TRUNC>
+    (float_truncate:<V_DOUBLE_TRUNC>
      (match_operand:VWEXTF_ZVFHMIN 1 "register_operand"      " vr")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
@@ -493,7 +493,7 @@
 ;; -------------------------------------------------------------------------
 (define_expand "trunc<mode><v_quad_trunc>2"
   [(set (match_operand:<V_QUAD_TRUNC> 0 "register_operand")
-    (truncate:<V_QUAD_TRUNC>
+    (float_truncate:<V_QUAD_TRUNC>
      (match_operand:VQEXTF 1 "register_operand")))]
   "TARGET_VECTOR && (TARGET_ZVFHMIN || TARGET_ZVFH)"
 {