* This could also be configured at run time using CPU freq framework. */
/* MDC Clock Selection define*/
-#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
-#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
-#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
-#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
-#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
-#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/124 */
-#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_scr_i/204 */
-#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_scr_i/324 */
+#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_csr_i/42 */
+#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_csr_i/62 */
+#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_csr_i/16 */
+#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_csr_i/26 */
+#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_csr_i/102 */
+#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_csr_i/124 */
+#define STMMAC_CSR_300_500M 0x6 /* MDC = clk_csr_i/204 */
+#define STMMAC_CSR_500_800M 0x7 /* MDC = clk_csr_i/324 */
/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR 0x0