u8 subordinate_bus;
u8 secondary_bus;
u32 cfg_control;
- u32 reg;
ft = resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS);
if (!ft)
CFG_CONTROL;
cfg_control = al_pcie_controller_readl(pcie, cfg_control_offset);
-
- reg = cfg_control &
- ~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
-
- reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
- FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
-
- al_pcie_controller_writel(pcie, cfg_control_offset, reg);
+ FIELD_MODIFY(CFG_CONTROL_SUBBUS_MASK, &cfg_control, subordinate_bus);
+ FIELD_MODIFY(CFG_CONTROL_SEC_BUS_MASK, &cfg_control, secondary_bus);
+ al_pcie_controller_writel(pcie, cfg_control_offset, cfg_control);
return 0;
}
return ret;
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG);
- val &= ~(LANE_SELECT);
- val |= FIELD_PREP(LANE_SELECT, lane);
+ FIELD_MODIFY(LANE_SELECT, &val, lane);
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + SD_STATUS_L1LANE_REG, val);
return count;
val |= ((err_inj_list[pdata->idx].err_inj_type << EINJ_TYPE_SHIFT) & type_mask);
val |= FIELD_PREP(EINJ_COUNT, counter);
- if (err_group == 1 || err_group == 4) {
- val &= ~(EINJ_VAL_DIFF);
- val |= FIELD_PREP(EINJ_VAL_DIFF, val_diff);
- }
- if (err_group == 4) {
- val &= ~(EINJ_VC_NUM);
- val |= FIELD_PREP(EINJ_VC_NUM, vc_num);
- }
+ if (err_group == 1 || err_group == 4)
+ FIELD_MODIFY(EINJ_VAL_DIFF, &val, val_diff);
+ if (err_group == 4)
+ FIELD_MODIFY(EINJ_VC_NUM, &val, vc_num);
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ0_OFF + (0x4 * err_group), val);
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + ERR_INJ_ENABLE_REG, (0x1 << err_group));
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
val &= ~EVENT_COUNTER_ENABLE;
- val &= ~(EVENT_COUNTER_GROUP_SELECT | EVENT_COUNTER_EVENT_SELECT);
- val |= FIELD_PREP(EVENT_COUNTER_GROUP_SELECT, event_list[pdata->idx].group_no);
- val |= FIELD_PREP(EVENT_COUNTER_EVENT_SELECT, event_list[pdata->idx].event_no);
+ FIELD_MODIFY(EVENT_COUNTER_GROUP_SELECT, &val, event_list[pdata->idx].group_no);
+ FIELD_MODIFY(EVENT_COUNTER_EVENT_SELECT, &val, event_list[pdata->idx].event_no);
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
}
mutex_lock(&rinfo->reg_event_lock);
set_event_number(pdata, pci, rinfo);
val = dw_pcie_readl_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG);
- val &= ~(EVENT_COUNTER_LANE_SELECT);
- val |= FIELD_PREP(EVENT_COUNTER_LANE_SELECT, lane);
+ FIELD_MODIFY(EVENT_COUNTER_LANE_SELECT, &val, lane);
dw_pcie_writel_dbi(pci, rinfo->ras_cap_offset + RAS_DES_EVENT_COUNTER_CTRL_REG, val);
mutex_unlock(&rinfo->reg_event_lock);
reg = ep_func->msi_cap + PCI_MSI_FLAGS;
val = dw_pcie_ep_readw_dbi(ep, func_no, reg);
- val &= ~PCI_MSI_FLAGS_QMASK;
- val |= FIELD_PREP(PCI_MSI_FLAGS_QMASK, mmc);
+ FIELD_MODIFY(PCI_MSI_FLAGS_QMASK, &val, mmc);
dw_pcie_dbi_ro_wr_en(pci);
dw_pcie_ep_writew_dbi(ep, func_no, reg, val);
dw_pcie_dbi_ro_wr_dis(pci);
cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP);
- lnkcap &= ~PCI_EXP_LNKCAP_MLW;
- lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, num_lanes);
+ FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, num_lanes);
dw_pcie_writel_dbi(pci, cap + PCI_EXP_LNKCAP, lnkcap);
}
/* Configure Root Port type */
val = readl_relaxed(pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
- val &= ~PCIEELBI_CTRL0_DEV_TYPE;
- val |= FIELD_PREP(PCIEELBI_CTRL0_DEV_TYPE, PCI_EXP_TYPE_ROOT_PORT);
+ FIELD_MODIFY(PCIEELBI_CTRL0_DEV_TYPE, &val, PCI_EXP_TYPE_ROOT_PORT);
writel_relaxed(val, pci->elbi_base + PCIEELBI_CTRL0_OFFSET);
list_for_each_entry(port, &pcie->ports, list) {
/* Set RP mode */
val = s32g_pcie_readl_ctrl(s32g_pp, PCIE_S32G_PE0_GEN_CTRL_1);
- val &= ~DEVICE_TYPE_MASK;
- val |= FIELD_PREP(DEVICE_TYPE_MASK, PCI_EXP_TYPE_ROOT_PORT);
+ FIELD_MODIFY(DEVICE_TYPE_MASK, &val, PCI_EXP_TYPE_ROOT_PORT);
/* Use default CRNS */
val &= ~SRIS_MODE;
reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
- reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
- reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,
- speed - PCIE_SPEED_8_0GT);
+ FIELD_MODIFY(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, ®,
+ speed - PCIE_SPEED_8_0GT);
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
- reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |
- GEN3_EQ_FMDC_N_EVALS |
- GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA |
- GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA);
- reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |
- FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |
- FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) |
- FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5);
+ FIELD_MODIFY(GEN3_EQ_FMDC_T_MIN_PHASE23, ®, 0x1);
+ FIELD_MODIFY(GEN3_EQ_FMDC_N_EVALS, ®, 0xd);
+ FIELD_MODIFY(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, ®, 0x5);
+ FIELD_MODIFY(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, ®, 0x5);
dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
u32 reg;
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
- reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
- MARGINING_NUM_VOLTAGE_STEPS |
- MARGINING_MAX_TIMING_OFFSET |
- MARGINING_NUM_TIMING_STEPS);
- reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
- FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
- FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
- FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
+ FIELD_MODIFY(MARGINING_MAX_VOLTAGE_OFFSET, ®, 0x24);
+ FIELD_MODIFY(MARGINING_NUM_VOLTAGE_STEPS, ®, 0x78);
+ FIELD_MODIFY(MARGINING_MAX_TIMING_OFFSET, ®, 0x32);
+ FIELD_MODIFY(MARGINING_NUM_TIMING_STEPS, ®, 0x10);
dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
MARGINING_SAMPLE_REPORTING_METHOD |
MARGINING_IND_LEFT_RIGHT_TIMING |
MARGINING_VOLTAGE_SUPPORTED;
- reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
- MARGINING_MAXLANES |
- MARGINING_SAMPLE_RATE_TIMING |
- MARGINING_SAMPLE_RATE_VOLTAGE);
- reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
- FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
- FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
+ reg &= ~MARGINING_IND_UP_DOWN_VOLTAGE;
+ FIELD_MODIFY(MARGINING_MAXLANES, ®, pci->num_lanes);
+ FIELD_MODIFY(MARGINING_SAMPLE_RATE_TIMING, ®, 0x3f);
+ FIELD_MODIFY(MARGINING_SAMPLE_RATE_VOLTAGE, ®, 0x3f);
dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
}
EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);
/* Set the L0s Exit Latency to 2us-4us = 0x6 */
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
- val &= ~PCI_EXP_LNKCAP_L0SEL;
- val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
+ FIELD_MODIFY(PCI_EXP_LNKCAP_L0SEL, &val, 0x6);
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
/* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
- val &= ~PCI_EXP_LNKCAP_L1EL;
- val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
+ FIELD_MODIFY(PCI_EXP_LNKCAP_L1EL, &val, 0x6);
dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
- val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC;
- val |= FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, 0x3ff);
+ FIELD_MODIFY(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, &val, 0x3ff);
val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE;
dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
- val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC;
- val |= FIELD_PREP(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC,
- pcie->of_data->gen4_preset_vec);
+ FIELD_MODIFY(GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC, &val,
+ pcie->of_data->gen4_preset_vec);
val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE;
dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
* not set correctly then link with endpoint card is not established.
*/
lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
- lnkcap &= ~PCI_EXP_LNKCAP_MLW;
- lnkcap |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, port->is_x4 ? 4 : 1);
+ FIELD_MODIFY(PCI_EXP_LNKCAP_MLW, &lnkcap, port->is_x4 ? 4 : 1);
mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
/* Disable Root Bridge I/O space, memory space and bus mastering. */
/* Set Link Control 2 (LNKCTL2) speed restriction, if any */
if (pcie->max_link_speed) {
val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);
- val &= ~PCIE_CONF_LINK2_LCR2_LINK_SPEED;
- val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);
+ FIELD_MODIFY(PCIE_CONF_LINK2_LCR2_LINK_SPEED, &val, pcie->max_link_speed);
writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);
}
pci_read_config_dword(pdev, pos + PCI_IDE_SEL_CTL, &val);
if (val & PCI_IDE_SEL_CTL_EN)
continue;
- val &= ~PCI_IDE_SEL_CTL_ID;
- val |= FIELD_PREP(PCI_IDE_SEL_CTL_ID, PCI_IDE_RESERVED_STREAM_ID);
+ FIELD_MODIFY(PCI_IDE_SEL_CTL_ID, &val, PCI_IDE_RESERVED_STREAM_ID);
pci_write_config_dword(pdev, pos + PCI_IDE_SEL_CTL, val);
}
pci_read_config_dword(pdev, pos, &val);
if (val & PCI_IDE_LINK_CTL_EN)
continue;
- val &= ~PCI_IDE_LINK_CTL_ID;
- val |= FIELD_PREP(PCI_IDE_LINK_CTL_ID, PCI_IDE_RESERVED_STREAM_ID);
+ FIELD_MODIFY(PCI_IDE_LINK_CTL_ID, &val, PCI_IDE_RESERVED_STREAM_ID);
pci_write_config_dword(pdev, pos, val);
}
pci_read_config_dword(dev, pos + PCI_VF_REBAR_CTRL, &ctrl);
bar_idx = FIELD_GET(PCI_VF_REBAR_CTRL_BAR_IDX, ctrl);
size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]);
- ctrl &= ~PCI_VF_REBAR_CTRL_BAR_SIZE;
- ctrl |= FIELD_PREP(PCI_VF_REBAR_CTRL_BAR_SIZE, size);
+ FIELD_MODIFY(PCI_VF_REBAR_CTRL_BAR_SIZE, &ctrl, size);
pci_write_config_dword(dev, pos + PCI_VF_REBAR_CTRL, ctrl);
}
}
u16 msgctl;
pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
- msgctl &= ~PCI_MSI_FLAGS_QSIZE;
- msgctl |= FIELD_PREP(PCI_MSI_FLAGS_QSIZE, desc->pci.msi_attrib.multiple);
+ FIELD_MODIFY(PCI_MSI_FLAGS_QSIZE, &msgctl, desc->pci.msi_attrib.multiple);
pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, msg->address_lo);
pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
pci_msi_update_mask(entry, 0, 0);
- control &= ~PCI_MSI_FLAGS_QSIZE;
- control |= PCI_MSI_FLAGS_ENABLE |
- FIELD_PREP(PCI_MSI_FLAGS_QSIZE, entry->pci.msi_attrib.multiple);
+ FIELD_MODIFY(PCI_MSI_FLAGS_QSIZE, &control, entry->pci.msi_attrib.multiple);
+ control |= PCI_MSI_FLAGS_ENABLE;
pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
}
if (!msi_desc || msi_desc->pci.msi_attrib.is_virtual)
return -ENXIO;
- msi_desc->pci.msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_ST;
- msi_desc->pci.msix_ctrl |= FIELD_PREP(PCI_MSIX_ENTRY_CTRL_ST, tag);
+ FIELD_MODIFY(PCI_MSIX_ENTRY_CTRL_ST, &msi_desc->pci.msix_ctrl, tag);
pci_msix_write_vector_ctrl(msi_desc, msi_desc->pci.msix_ctrl);
/* Flush the write */
readl(pci_msix_desc_addr(msi_desc));
if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
return -EIO;
- cmd &= ~PCI_X_CMD_MAX_READ;
- cmd |= FIELD_PREP(PCI_X_CMD_MAX_READ, v);
+ FIELD_MODIFY(PCI_X_CMD_MAX_READ, &cmd, v);
if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
return -EIO;
}
pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
ctrl |= PCI_PTM_CTRL_ENABLE;
- ctrl &= ~PCI_PTM_GRANULARITY_MASK;
- ctrl |= FIELD_PREP(PCI_PTM_GRANULARITY_MASK, dev->ptm_granularity);
+ FIELD_MODIFY(PCI_PTM_GRANULARITY_MASK, &ctrl, dev->ptm_granularity);
if (dev->ptm_root)
ctrl |= PCI_PTM_CTRL_ROOT;
return pos;
pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
- ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
- ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
+ FIELD_MODIFY(PCI_REBAR_CTRL_BAR_SIZE, &ctrl, size);
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
if (pci_resource_is_iov(bar))
bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
res = pci_resource_n(pdev, bar_idx);
size = pci_rebar_bytes_to_size(resource_size(res));
- ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
- ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size);
+ FIELD_MODIFY(PCI_REBAR_CTRL_BAR_SIZE, &ctrl, size);
pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
}
}
* yenta.c forces a secondary latency timer of 176.
* Copy that behaviour here.
*/
- buses &= ~PCI_SEC_LATENCY_TIMER_MASK;
- buses |= FIELD_PREP(PCI_SEC_LATENCY_TIMER_MASK, CARDBUS_LATENCY_TIMER);
+ FIELD_MODIFY(PCI_SEC_LATENCY_TIMER_MASK, &buses, CARDBUS_LATENCY_TIMER);
/* We need to blast all three values with a single write */
pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, ®);
- reg &= ~PCI_TPH_CTRL_REQ_EN_MASK;
- reg |= FIELD_PREP(PCI_TPH_CTRL_REQ_EN_MASK, req_type);
+ FIELD_MODIFY(PCI_TPH_CTRL_REQ_EN_MASK, ®, req_type);
pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);
}
/* Write them into TPH control register */
pci_read_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, ®);
- reg &= ~PCI_TPH_CTRL_MODE_SEL_MASK;
- reg |= FIELD_PREP(PCI_TPH_CTRL_MODE_SEL_MASK, pdev->tph_mode);
-
- reg &= ~PCI_TPH_CTRL_REQ_EN_MASK;
- reg |= FIELD_PREP(PCI_TPH_CTRL_REQ_EN_MASK, pdev->tph_req_type);
+ FIELD_MODIFY(PCI_TPH_CTRL_MODE_SEL_MASK, ®, pdev->tph_mode);
+ FIELD_MODIFY(PCI_TPH_CTRL_REQ_EN_MASK, ®, pdev->tph_req_type);
pci_write_config_dword(pdev, pdev->tph_cap + PCI_TPH_CTRL, reg);
projects / thirdparty / linux.git / commitdiff
