#include <linux/serial_core.h>
#include <linux/serial_sci.h>
#include <linux/tty_flip.h>
+
+#include "serial_mctrl_gpio.h"
#include "rsci.h"
MODULE_IMPORT_NS("SH_SCI");
#define CCR1_CTSPEN BIT(1) /* CTS External Pin Enable */
#define CCR1_CTSE BIT(0) /* CTS Enable */
+/* CCR2 (Common Control Register 2) */
+#define CCR2_INIT 0xFF000004
+#define CCR2_CKS_TCLK (0) /* TCLK clock */
+#define CCR2_CKS_TCLK_DIV4 BIT(20) /* TCLK/4 clock */
+#define CCR2_CKS_TCLK_DIV16 BIT(21) /* TCLK16 clock */
+#define CCR2_CKS_TCLK_DIV64 (BIT(21) | BIT(20)) /* TCLK/64 clock */
+#define CCR2_BRME BIT(16) /* Bitrate Modulation Enable */
+#define CCR2_ABCSE BIT(6) /* Asynchronous Mode Extended Base Clock Select */
+#define CCR2_ABCS BIT(5) /* Asynchronous Mode Base Clock Select */
+#define CCR2_BGDM BIT(4) /* Baud Rate Generator Double-Speed Mode Select */
+
+/* CCR3 (Common Control Register 3) */
+#define CCR3_INIT 0x1203
+#define CCR3_BLK BIT(29) /* Block Transfer Mode */
+#define CCR3_GM BIT(28) /* GSM Mode */
+#define CCR3_CKE1 BIT(25) /* Clock Enable 1 */
+#define CCR3_CKE0 BIT(24) /* Clock Enable 0 */
+#define CCR3_DEN BIT(21) /* Driver Enabled */
+#define CCR3_FM BIT(20) /* FIFO Mode Select */
+#define CCR3_MP BIT(19) /* Multi-Processor Mode */
+#define CCR3_MOD_ASYNC 0 /* Asynchronous mode (Multi-processor mode) */
+#define CCR3_MOD_IRDA BIT(16) /* Smart card interface mode */
+#define CCR3_MOD_CLK_SYNC BIT(17) /* Clock synchronous mode */
+#define CCR3_MOD_SPI (BIT(17) | BIT(16)) /* Simple SPI mode */
+#define CCR3_MOD_I2C BIT(18) /* Simple I2C mode */
+#define CCR3_RXDESEL BIT(15) /* Asynchronous Start Bit Edge Detection Select */
+#define CCR3_STP BIT(14) /* Stop bit Length */
+#define CCR3_SINV BIT(13) /* Transmitted/Received Data Invert */
+#define CCR3_LSBF BIT(12) /* LSB First select */
+#define CCR3_CHR1 BIT(9) /* Character Length */
+#define CCR3_CHR0 BIT(8) /* Character Length */
+#define CCR3_BPEN BIT(7) /* Synchronizer Bypass Enable */
+#define CCR3_CPOL BIT(1) /* Clock Polarity Select */
+#define CCR3_CPHA BIT(0) /* Clock Phase Select */
+
/* FCR (FIFO Control Register) */
#define FCR_RFRST BIT(23) /* Receive FIFO Data Register Reset */
#define FCR_TFRST BIT(15) /* Transmit FIFO Data Register Reset */
rsci_serial_out(port, CCR0, ctrl);
}
+static void rsci_enable_ms(struct uart_port *port)
+{
+ mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
+}
+
+static void rsci_init_pins(struct uart_port *port, unsigned int cflag)
+{
+ struct sci_port *s = to_sci_port(port);
+
+ /* Use port-specific handler if provided */
+ if (s->cfg->ops && s->cfg->ops->init_pins) {
+ s->cfg->ops->init_pins(port, cflag);
+ return;
+ }
+
+ if (!s->has_rtscts)
+ return;
+
+ if (s->autorts)
+ rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) |
+ CCR1_CTSE | CCR1_CTSPEN);
+}
+
static int rsci_scif_set_rtrg(struct uart_port *port, int rx_trig)
{
u32 fcr = rsci_serial_in(port, FCR);
static void rsci_set_termios(struct uart_port *port, struct ktermios *termios,
const struct ktermios *old)
{
+ unsigned int ccr2_val = CCR2_INIT, ccr3_val = CCR3_INIT;
+ unsigned int ccr0_val = 0, ccr1_val = 0, ccr4_val = 0;
+ unsigned int brr1 = 255, cks1 = 0, srr1 = 15;
struct sci_port *s = to_sci_port(port);
+ unsigned int brr = 255, cks = 0;
+ int min_err = INT_MAX, err;
+ unsigned long max_freq = 0;
+ unsigned int baud, i;
unsigned long flags;
+ unsigned int ctrl;
+ int best_clk = -1;
+
+ if ((termios->c_cflag & CSIZE) == CS7) {
+ ccr3_val |= CCR3_CHR0;
+ } else {
+ termios->c_cflag &= ~CSIZE;
+ termios->c_cflag |= CS8;
+ }
+
+ if (termios->c_cflag & PARENB)
+ ccr1_val |= CCR1_PE;
+
+ if (termios->c_cflag & PARODD)
+ ccr1_val |= (CCR1_PE | CCR1_PM);
+
+ if (termios->c_cflag & CSTOPB)
+ ccr3_val |= CCR3_STP;
+
+ /* Enable noise filter function */
+ ccr1_val |= CCR1_NFEN;
+
+ /*
+ * earlyprintk comes here early on with port->uartclk set to zero.
+ * the clock framework is not up and running at this point so here
+ * we assume that 115200 is the maximum baud rate. please note that
+ * the baud rate is not programmed during earlyprintk - it is assumed
+ * that the previous boot loader has enabled required clocks and
+ * setup the baud rate generator hardware for us already.
+ */
+ if (!port->uartclk) {
+ max_freq = 115200;
+ } else {
+ for (i = 0; i < SCI_NUM_CLKS; i++)
+ max_freq = max(max_freq, s->clk_rates[i]);
+
+ max_freq /= min_sr(s);
+ }
+
+ baud = uart_get_baud_rate(port, termios, old, 0, max_freq);
+ if (!baud)
+ goto done;
+
+ /* Divided Functional Clock using standard Bit Rate Register */
+ err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
+ if (abs(err) < abs(min_err)) {
+ best_clk = SCI_FCK;
+ ccr0_val = 0;
+ min_err = err;
+ brr = brr1;
+ cks = cks1;
+ }
+
+done:
+ if (best_clk >= 0)
+ dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
+ s->clks[best_clk], baud, min_err);
sci_port_enable(s);
uart_port_lock_irqsave(port, &flags);
- /* For now, only RX enabling is supported */
- if (termios->c_cflag & CREAD)
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ rsci_serial_out(port, CCR0, ccr0_val);
+
+ ccr3_val |= CCR3_FM;
+ rsci_serial_out(port, CCR3, ccr3_val);
+
+ ccr2_val |= (cks << 20) | (brr << 8);
+ rsci_serial_out(port, CCR2, ccr2_val);
+
+ rsci_serial_out(port, CCR1, ccr1_val);
+ rsci_serial_out(port, CCR4, ccr4_val);
+
+ ctrl = rsci_serial_in(port, FCR);
+ ctrl |= (FCR_RFRST | FCR_TFRST);
+ rsci_serial_out(port, FCR, ctrl);
+
+ if (s->rx_trigger > 1)
+ rsci_scif_set_rtrg(port, s->rx_trigger);
+
+ port->status &= ~UPSTAT_AUTOCTS;
+ s->autorts = false;
+
+ if ((port->flags & UPF_HARD_FLOW) && (termios->c_cflag & CRTSCTS)) {
+ port->status |= UPSTAT_AUTOCTS;
+ s->autorts = true;
+ }
+
+ rsci_init_pins(port, termios->c_cflag);
+ rsci_serial_out(port, CFCLR, CFCLR_CLRFLAG);
+ rsci_serial_out(port, FFCLR, FFCLR_DRC);
+
+ ccr0_val |= CCR0_RE;
+ rsci_serial_out(port, CCR0, ccr0_val);
+
+ if ((termios->c_cflag & CREAD) != 0)
rsci_start_rx(port);
uart_port_unlock_irqrestore(port, flags);
sci_port_disable(s);
+
+ if (UART_ENABLE_MS(port, termios->c_cflag))
+ rsci_enable_ms(port);
}
static int rsci_txfill(struct uart_port *port)
static void rsci_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
- /* Not supported yet */
+ if (mctrl & TIOCM_LOOP) {
+ /* Standard loopback mode */
+ rsci_serial_out(port, CCR1, rsci_serial_in(port, CCR1) | CCR1_SPLP);
+ }
}
static unsigned int rsci_get_mctrl(struct uart_port *port)
{
- /* Not supported yet */
- return 0;
+ struct sci_port *s = to_sci_port(port);
+ struct mctrl_gpios *gpios = s->gpios;
+ unsigned int mctrl = 0;
+
+ mctrl_gpio_get(gpios, &mctrl);
+
+ /*
+ * CTS/RTS is handled in hardware when supported, while nothing
+ * else is wired up.
+ */
+ if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))
+ mctrl |= TIOCM_CTS;
+
+ if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
+ mctrl |= TIOCM_DSR;
+
+ if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
+ mctrl |= TIOCM_CAR;
+
+ return mctrl;
}
static void rsci_clear_CFC(struct uart_port *port, unsigned int mask)
continue;
}
- /* Store data and status.
+ /*
+ * Store data and status.
* Non FIFO mode is not supported
*/
if (rdat & RDR_FFER) {
}
}
+static void rsci_break_ctl(struct uart_port *port, int break_state)
+{
+ unsigned short ccr0_val, ccr1_val;
+ unsigned long flags;
+
+ uart_port_lock_irqsave(port, &flags);
+ ccr1_val = rsci_serial_in(port, CCR1);
+ ccr0_val = rsci_serial_in(port, CCR0);
+
+ if (break_state == -1) {
+ ccr1_val = (ccr1_val | CCR1_SPB2IO) & ~CCR1_SPB2DT;
+ ccr0_val &= ~CCR0_TE;
+ } else {
+ ccr1_val = (ccr1_val | CCR1_SPB2DT) & ~CCR1_SPB2IO;
+ ccr0_val |= CCR0_TE;
+ }
+
+ rsci_serial_out(port, CCR1, ccr1_val);
+ rsci_serial_out(port, CCR0, ccr0_val);
+ uart_port_unlock_irqrestore(port, flags);
+}
+
static void rsci_poll_put_char(struct uart_port *port, unsigned char c)
{
u32 status;
static void rsci_prepare_console_write(struct uart_port *port, u32 ctrl)
{
struct sci_port *s = to_sci_port(port);
- u32 ctrl_temp =
- s->params->param_bits->rxtx_enable | CCR0_TIE |
- s->hscif_tot;
+ u32 ctrl_temp = s->params->param_bits->rxtx_enable;
+
+ if (s->type == RSCI_PORT_SCIF16)
+ ctrl_temp |= CCR0_TIE | s->hscif_tot;
+
rsci_serial_out(port, CCR0, ctrl_temp);
}
+static void rsci_finish_console_write(struct uart_port *port, u32 ctrl)
+{
+ /* First set TE = 0 and then restore the CCR0 value */
+ rsci_serial_out(port, CCR0, ctrl & ~CCR0_TE);
+ rsci_serial_out(port, CCR0, ctrl);
+}
+
static const char *rsci_type(struct uart_port *port)
{
return "rsci";
.poll_sent_bits = CSR_TDRE | CSR_TEND,
};
+static const struct sci_port_params rsci_rzg3e_port_params = {
+ .fifosize = 32,
+ .overrun_reg = CSR,
+ .overrun_mask = CSR_ORER,
+ .sampling_rate_mask = SCI_SR(32),
+ .error_mask = RSCI_DEFAULT_ERROR_MASK,
+ .error_clear = RSCI_ERROR_CLEAR,
+ .param_bits = &rsci_port_param_bits,
+ .common_regs = &rsci_common_regs,
+};
+
static const struct sci_port_params rsci_rzt2h_port_params = {
.fifosize = 16,
.overrun_reg = CSR,
.start_tx = rsci_start_tx,
.stop_tx = rsci_stop_tx,
.stop_rx = rsci_stop_rx,
+ .enable_ms = rsci_enable_ms,
+ .break_ctl = rsci_break_ctl,
.startup = sci_startup,
.shutdown = sci_shutdown,
.set_termios = rsci_set_termios,
.receive_chars = rsci_receive_chars,
.poll_put_char = rsci_poll_put_char,
.prepare_console_write = rsci_prepare_console_write,
+ .finish_console_write = rsci_finish_console_write,
.suspend_regs_size = rsci_suspend_regs_size,
.set_rtrg = rsci_scif_set_rtrg,
.shutdown_complete = rsci_shutdown_complete,
};
+struct sci_of_data of_rsci_rzg3e_data = {
+ .type = RSCI_PORT_SCIF32,
+ .ops = &rsci_port_ops,
+ .uart_ops = &rsci_uart_ops,
+ .params = &rsci_rzg3e_port_params,
+};
+
struct sci_of_data of_rsci_rzt2h_data = {
.type = RSCI_PORT_SCIF16,
.ops = &rsci_port_ops,
#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
+static int __init rsci_rzg3e_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ return scix_early_console_setup(device, &of_rsci_rzg3e_data);
+}
+
static int __init rsci_rzt2h_early_console_setup(struct earlycon_device *device,
const char *opt)
{
return scix_early_console_setup(device, &of_rsci_rzt2h_data);
}
+OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g047-rsci", rsci_rzg3e_early_console_setup);
OF_EARLYCON_DECLARE(rsci, "renesas,r9a09g077-rsci", rsci_rzt2h_early_console_setup);
#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
projects / thirdparty / kernel / linux.git / commitdiff
