perf/x86/intel: Update event constraints and cache_extra_regsfor NVL

Update perf hard-coded event constraints and cache_extra_regs[] for
Novalake according to the latest NVL perfmon events.

The 4 PRECISE_OMR events (0xd4) are broken on Arcticwolf and would be
removed from upcoming released event list, so delete them from event
constraints and extra_regs array accordingly.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260515061143.338553-10-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 60a107c5b4d0f012f152dcd287d5154569c401c1..332761d253731c46c6468ca5480abd846a3cc18f 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -241,20 +241,21 @@ static struct event_constraint intel_skt_event_constraints[] __read_mostly = {
 
 static struct event_constraint intel_arw_event_constraints[] __read_mostly = {
        FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
+       FIXED_EVENT_CONSTRAINT(0x0100, 0), /* pseudo INST_RETIRED.ANY */
        FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
-       FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
+       FIXED_EVENT_CONSTRAINT(0x0200, 1), /* pseudo CPU_CLK_UNHALTED.THREAD */
+       FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF_TSC */
        FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF_TSC_P */
        FIXED_EVENT_CONSTRAINT(0x0073, 4), /* TOPDOWN_BAD_SPECULATION.ALL */
+       FIXED_EVENT_CONSTRAINT(0x0500, 4), /* pseudo TOPDOWN_BAD_SPECULATION.ALL */
        FIXED_EVENT_CONSTRAINT(0x019c, 5), /* TOPDOWN_FE_BOUND.ALL */
+       FIXED_EVENT_CONSTRAINT(0x0600, 5), /* pseudo TOPDOWN_FE_BOUND.ALL */
        FIXED_EVENT_CONSTRAINT(0x02c2, 6), /* TOPDOWN_RETIRING.ALL */
+       FIXED_EVENT_CONSTRAINT(0x0700, 6), /* pseudo TOPDOWN_RETIRING.ALL */
        INTEL_UEVENT_CONSTRAINT(0x01b7, 0x1),
        INTEL_UEVENT_CONSTRAINT(0x02b7, 0x2),
        INTEL_UEVENT_CONSTRAINT(0x04b7, 0x4),
        INTEL_UEVENT_CONSTRAINT(0x08b7, 0x8),
-       INTEL_UEVENT_CONSTRAINT(0x01d4, 0x1),
-       INTEL_UEVENT_CONSTRAINT(0x02d4, 0x2),
-       INTEL_UEVENT_CONSTRAINT(0x04d4, 0x4),
-       INTEL_UEVENT_CONSTRAINT(0x08d4, 0x8),
        INTEL_UEVENT_CONSTRAINT(0x0175, 0x1),
        INTEL_UEVENT_CONSTRAINT(0x0275, 0x2),
        INTEL_UEVENT_CONSTRAINT(0x21d3, 0x1),
@@ -964,6 +965,23 @@ static __initconst const u64 pnc_hw_cache_extra_regs
  },
 };
 
+static __initconst const u64 cyc_hw_cache_extra_regs
+                               [PERF_COUNT_HW_CACHE_MAX]
+                               [PERF_COUNT_HW_CACHE_OP_MAX]
+                               [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL  ) ] = {
+       [ C(OP_READ) ] = {
+               [ C(RESULT_ACCESS) ] = 0x4000000000000001,      /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
+               [ C(RESULT_MISS)   ] = 0xFF03F000000001,        /* OMR.DEMAND_DATA_RD.L3_MISS */
+       },
+       [ C(OP_WRITE) ] = {
+               [ C(RESULT_ACCESS) ] = 0x4000000000000002,      /* OMR.DEMAND_RFO.ANY_RESPONSE */
+               [ C(RESULT_MISS)   ] = 0xFF03F000000002,        /* OMR.DEMAND_RFO.L3_MISS */
+       },
+ },
+};
+
 /*
  * Notes on the events:
  * - data reads do not include code reads (comparable to earlier tables)
@@ -2570,16 +2588,12 @@ static __initconst const u64 arw_hw_cache_extra_regs
                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
        [C(LL)] = {
                [C(OP_READ)] = {
-                       [C(RESULT_ACCESS)]      = 0x4000000000000001,
-                       [C(RESULT_MISS)]        = 0xFFFFF000000001,
+                       [C(RESULT_ACCESS)]      = 0x4000000000000009,   /* OMR.DEMAND_DATA_RD.ANY_RESPONSE */
+                       [C(RESULT_MISS)]        = 0xFF03F000000009,     /* OMR.DEMAND_DATA_RD.L3_MISS */
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)]      = 0x4000000000000002,
-                       [C(RESULT_MISS)]        = 0xFFFFF000000002,
-               },
-               [C(OP_PREFETCH)] = {
-                       [C(RESULT_ACCESS)]      = 0x0,
-                       [C(RESULT_MISS)]        = 0x0,
+                       [C(RESULT_ACCESS)]      = 0x400000000000000A,   /* OMR.DEMAND_RFO.ANY_RESPONSE */
+                       [C(RESULT_MISS)]        = 0xFF03F00000000A,     /* OMR.DEMAND_RFO.L3_MISS */
                },
        },
 };
@@ -2651,10 +2665,6 @@ static struct extra_reg intel_arw_extra_regs[] __read_mostly = {
        INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
        INTEL_UEVENT_EXTRA_REG(0x04b7, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
        INTEL_UEVENT_EXTRA_REG(0x08b7, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
-       INTEL_UEVENT_EXTRA_REG(0x01d4, MSR_OMR_0, 0xc0ffffffffffffffull, OMR_0),
-       INTEL_UEVENT_EXTRA_REG(0x02d4, MSR_OMR_1, 0xc0ffffffffffffffull, OMR_1),
-       INTEL_UEVENT_EXTRA_REG(0x04d4, MSR_OMR_2, 0xc0ffffffffffffffull, OMR_2),
-       INTEL_UEVENT_EXTRA_REG(0x08d4, MSR_OMR_3, 0xc0ffffffffffffffull, OMR_3),
        INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x5d0),
        INTEL_UEVENT_EXTRA_REG(0x0127, MSR_SNOOP_RSP_0, 0xffffffffffffffffull, SNOOP_0),
        INTEL_UEVENT_EXTRA_REG(0x0227, MSR_SNOOP_RSP_1, 0xffffffffffffffffull, SNOOP_1),
@@ -7781,6 +7791,13 @@ static __always_inline void intel_pmu_init_pnc(struct pmu *pmu)
        static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
 }
 
+static __always_inline void intel_pmu_init_cyc(struct pmu *pmu)
+{
+       intel_pmu_init_pnc(pmu);
+       memcpy(hybrid_var(pmu, hw_cache_extra_regs),
+              cyc_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
+}
+
 static __always_inline void intel_pmu_init_skt(struct pmu *pmu)
 {
        intel_pmu_init_cmt(pmu);
@@ -7805,7 +7822,7 @@ static __always_inline void intel_pmu_init_arw(struct pmu *pmu)
        memcpy(hybrid_var(pmu, hw_cache_extra_regs),
               arw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
        hybrid(pmu, event_constraints) = intel_arw_event_constraints;
-       hybrid(pmu, pebs_constraints) = intel_arw_pebs_event_constraints;
+       hybrid(pmu, pebs_constraints) = intel_dkt_pebs_event_constraints;
        hybrid(pmu, extra_regs) = intel_arw_extra_regs;
        static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr);
 }
@@ -8696,7 +8713,7 @@ __init int intel_pmu_init(void)
 
                /* Initialize big core specific PerfMon capabilities.*/
                pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX];
-               intel_pmu_init_pnc(&pmu->pmu);
+               intel_pmu_init_cyc(&pmu->pmu);
 
                /* Initialize Atom core specific PerfMon capabilities.*/
                pmu = &x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX];

diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 5159adabb9a2022f2a35299a5574991aa3db262f..cb72af9b61cee817c023854c33f6e4e590fde1a6 100644 (file)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1310,17 +1310,6 @@ struct event_constraint intel_dkt_pebs_event_constraints[] = {
        EVENT_CONSTRAINT_END
 };
 
-struct event_constraint intel_arw_pebs_event_constraints[] = {
-       /* Allow all events as PEBS with no flags */
-       INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xff),
-       INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xff),
-       INTEL_FLAGS_UEVENT_CONSTRAINT(0x01d4, 0x1),
-       INTEL_FLAGS_UEVENT_CONSTRAINT(0x02d4, 0x2),
-       INTEL_FLAGS_UEVENT_CONSTRAINT(0x04d4, 0x4),
-       INTEL_FLAGS_UEVENT_CONSTRAINT(0x08d4, 0x8),
-       EVENT_CONSTRAINT_END
-};
-
 struct event_constraint intel_nehalem_pebs_event_constraints[] = {
        INTEL_PLD_CONSTRAINT(0x100b, 0xf),      /* MEM_INST_RETIRED.* */
        INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),    /* MEM_UNCORE_RETIRED.* */

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 982864c7a06412559e643525ec06e94d4a38572b..eae24bb35dc149aa851bbb2f73d9e8913f1c18e2 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -1714,8 +1714,6 @@ extern struct event_constraint intel_cmt_pebs_event_constraints[];
 
 extern struct event_constraint intel_dkt_pebs_event_constraints[];
 
-extern struct event_constraint intel_arw_pebs_event_constraints[];
-
 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
 
 extern struct event_constraint intel_westmere_pebs_event_constraints[];