gpio: aspeed-sgpio: Convert IRQ functions to use llops callbacks

Update aspeed_sgpio_irq_handler() and aspeed_sgpio_setup_irqs() to use
the llops callbacks for register access instead of direct iowrite32().
This creates a unified hardware access layer, which is essential for
supporting SoCs with different register layouts like the AST2700.

Additionally, change the loop bounds to use ngpio instead of the static
ARRAY_SIZE(aspeed_sgpio_banks). This allows the driver to adapt to the
actual number of supported pins on the running SoC.

Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
Link: https://lore.kernel.org/r/20260123-upstream_sgpio-v2-4-69cfd1631400@aspeedtech.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>

diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 33a830ea7d28d7ef952bae6429e21a21d1bdf64f..b5270e11b153d38e46643028819943d7475d8cd5 100644 (file)
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -319,12 +319,13 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
        struct gpio_chip *gc = irq_desc_get_handler_data(desc);
        struct irq_chip *ic = irq_desc_get_chip(desc);
        struct aspeed_sgpio *data = gpiochip_get_data(gc);
-       unsigned int i, p;
+       unsigned int i, p, banks;
        unsigned long reg;
 
        chained_irq_enter(ic, desc);
 
-       for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
+       banks = DIV_ROUND_UP(gc->ngpio, 64);
+       for (i = 0; i < banks; i++) {
                reg = data->pdata->llops->reg_bank_get(data, i << 6, reg_irq_status);
 
                for_each_set_bit(p, &reg, 32)
@@ -355,7 +356,6 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
                                   struct platform_device *pdev)
 {
        int rc, i;
-       const struct aspeed_sgpio_bank *bank;
        struct gpio_irq_chip *irq;
 
        rc = platform_get_irq(pdev, 0);
@@ -365,12 +365,11 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
        gpio->irq = rc;
 
        /* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
-       for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
-               bank =  &aspeed_sgpio_banks[i];
+       for (i = 0; i < gpio->chip.ngpio; i += 2) {
                /* disable irq enable bits */
-               iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
+               gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_enable, 0);
                /* clear status bits */
-               iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
+               gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_status, 1);
        }
 
        irq = &gpio->chip.irq;
@@ -384,14 +383,13 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
        irq->num_parents = 1;
 
        /* Apply default IRQ settings */
-       for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
-               bank =  &aspeed_sgpio_banks[i];
+       for (i = 0; i < gpio->chip.ngpio; i += 2) {
                /* set falling or level-low irq */
-               iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
+               gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type0, 0);
                /* trigger type is edge */
-               iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
+               gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type1, 0);
                /* single edge trigger */
-               iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
+               gpio->pdata->llops->reg_bit_set(gpio, i, reg_irq_type2, 0);
        }
 
        return 0;