Re-enable RET $imm16 following insn decoding framework rework.

Fixes #292430 (a regression).

git-svn-id: svn://svn.valgrind.org/vex/trunk@2255

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index 1beca986d377879bd92a5afc1a16f0fcca4ec792..a8ba1d4e58bd01760fc8d01e3293214d93d01c3a 100644 (file)
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -17432,6 +17432,15 @@ Long dis_ESC_NONE (
       return delta;
    }
 
+   case 0xC2: /* RET imm16 */
+      if (have66orF2orF3(pfx)) goto decode_failure;
+      d64 = getUDisp16(delta); 
+      delta += 2;
+      dis_ret(vbi, d64);
+      dres->whatNext = Dis_StopHere;
+      DIP("ret $%lld\n", d64);
+      return delta;
+
    case 0xC3: /* RET */
       if (have66orF2(pfx)) goto decode_failure;
       /* F3 is acceptable on AMD. */
@@ -19153,15 +19162,6 @@ DisResult disInstr_AMD64_WRK (
 
    /* ------------------------ Control flow --------------- */
 
-   case 0xC2: /* RET imm16 */
-      if (have66orF2orF3(pfx)) goto decode_failure;
-      d64 = getUDisp16(delta); 
-      delta += 2;
-      dis_ret(vbi, d64);
-      dres.whatNext = Dis_StopHere;
-      DIP("ret %lld\n", d64);
-      break;
-
    /* ------------------------ CWD/CDQ -------------------- */
 
    /* ------------------------ FPU ops -------------------- */