PCI: xilinx-cpm: Add cpm_csr register mapping for CPM5_HOST1 variant

[ Upstream commit 9e141923cf86b2e1c83d21b87fb4de3d14a20c99 ]

Update the CPM5 check to include CPM5_HOST1 variant. Previously, only
CPM5 was considered when mapping the "cpm_csr" register.

With this change, CPM5_HOST1 is also supported, ensuring proper
resource mapping for this variant.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Link: https://lore.kernel.org/r/20250317124136.1317723-1-thippeswamy.havalige@amd.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index dc8ecdbee56c89c0e9c21ca11981b70c9168933b..163d805673d6dd4486ea18e1676f68f2cb08c6cc 100644 (file)
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -538,7 +538,8 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
        if (IS_ERR(port->cfg))
                return PTR_ERR(port->cfg);
 
-       if (port->variant->version == CPM5) {
+       if (port->variant->version == CPM5 ||
+           port->variant->version == CPM5_HOST1) {
                port->reg_base = devm_platform_ioremap_resource_byname(pdev,
                                                                    "cpm_csr");
                if (IS_ERR(port->reg_base))