ASoC: fsl_xcvr: get channel status data when PHY is not exists

commit ca592e20659e0304ebd8f4dabb273da4f9385848 upstream.

There is no PHY for the XCVR module on i.MX93, the channel status needs
to be obtained from FSL_XCVR_RX_CS_DATA_* registers. And channel status
acknowledge (CSA) bit should be set once channel status is processed.

Fixes: e240b9329a30 ("ASoC: fsl_xcvr: Add support for i.MX93 platform")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/20250710030405.3370671-2-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c
index 8065fa5c95e1018b2466eed39f5506aa0f7c0f84..ae5960b2b6a951d0f1f6059235606e35f8876ffb 100644 (file)
--- a/sound/soc/fsl/fsl_xcvr.c
+++ b/sound/soc/fsl/fsl_xcvr.c
@@ -1165,6 +1165,26 @@ static irqreturn_t irq0_isr(int irq, void *devid)
                                /* clear CS control register */
                                writel_relaxed(0, reg_ctrl);
                        }
+               } else {
+                       regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0,
+                                   (u32 *)&xcvr->rx_iec958.status[0]);
+                       regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1,
+                                   (u32 *)&xcvr->rx_iec958.status[4]);
+                       regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2,
+                                   (u32 *)&xcvr->rx_iec958.status[8]);
+                       regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3,
+                                   (u32 *)&xcvr->rx_iec958.status[12]);
+                       regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4,
+                                   (u32 *)&xcvr->rx_iec958.status[16]);
+                       regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5,
+                                   (u32 *)&xcvr->rx_iec958.status[20]);
+                       for (i = 0; i < 6; i++) {
+                               val = *(u32 *)(xcvr->rx_iec958.status + i * 4);
+                               *(u32 *)(xcvr->rx_iec958.status + i * 4) =
+                                       bitrev32(val);
+                       }
+                       regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL,
+                                       FSL_XCVR_RX_DPTH_CTRL_CSA);
                }
        }
        if (isr & FSL_XCVR_IRQ_NEW_UD) {