Fix bogus RTL on the H8.

This patch actually fixes the bogus RTL seen in PR101697.

Basically we continue to use the insn condition to catch most of the problem
cases related to autoinc addressing modes.  This patch adds constraints which
can guide reload (and hopefully LRA) away from doing blind replacements during
register elimination that would ultimately result in bogus RTL.  The idea is
from Paul K. who has done something very similar on the pdp11.  I guess it
shouldn't be a big surprise that the H8 and pdp11 need the same kind of
handling given some of the similarities in their architectures.

gcc/
	PR target/101697
	* config/h8300/combiner.md: Replace '<' preincment constraint with
	ZA/Z1..ZH/Z7 combinations.
	* config/h8300/movepush.md: Similarly

diff --git a/gcc/config/h8300/combiner.md b/gcc/config/h8300/combiner.md
index 067f26678c1e8c5eb8cceff2ae5f64a555ae73ae..fd5cf2f4af4aa068686093803a01d49df3109000 100644 (file)
--- a/gcc/config/h8300/combiner.md
+++ b/gcc/config/h8300/combiner.md
@@ -1142,8 +1142,8 @@
 ;; Storing a part of HImode to QImode.
 
 (define_insn_and_split ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh")
+       (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 8)) 1))]
   ""
   "#"
@@ -1153,8 +1153,8 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg")
+       (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 8)) 1))
    (clobber (reg:CC CC_REG))]
   ""
@@ -1164,8 +1164,8 @@
 ;; Storing a part of SImode to QImode.
 
 (define_insn_and_split ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg")
+       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 8)) 3))]
   ""
   "#"
@@ -1175,8 +1175,8 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg")
+       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 8)) 3))
    (clobber (reg:CC CC_REG))]
   ""
@@ -1184,10 +1184,10 @@
   [(set_attr "length" "8")])
 
 (define_insn_and_split ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg")
+       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 16)) 3))
-   (clobber (match_scratch:SI 2 "=&r"))]
+   (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
   ""
   "#"
   "&& reload_completed"
@@ -1197,20 +1197,20 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg")
+       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 16)) 3))
-   (clobber (match_scratch:SI 2 "=&r"))
+   (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r"))
    (clobber (reg:CC CC_REG))]
   ""
   "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0"
   [(set_attr "length" "10")])
 
 (define_insn_and_split ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg")
+       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 24)) 3))
-   (clobber (match_scratch:SI 2 "=&r"))]
+   (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
   ""
   "#"
   "&& reload_completed"
@@ -1220,10 +1220,10 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn ""
-  [(set (match_operand:QI 0 "general_operand_dst" "=rm<")
-       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
+  [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg")
+       (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7")
                                (const_int 24)) 3))
-   (clobber (match_scratch:SI 2 "=&r"))
+   (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r"))
    (clobber (reg:CC CC_REG))]
   ""
   "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0"

diff --git a/gcc/config/h8300/movepush.md b/gcc/config/h8300/movepush.md
index e895de8ce596a3d63996ae890aed1f24ab7c3f96..e536602a01d6ecb4ef2385aabc002bc87084ff57 100644 (file)
--- a/gcc/config/h8300/movepush.md
+++ b/gcc/config/h8300/movepush.md
@@ -5,8 +5,8 @@
 ;; movqi
 
 (define_insn_and_split "*movqi"
-  [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
-       (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))]
+  [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m")
+       (match_operand:QI 1 "general_operand_src" " I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,n,m,r"))]
   "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])"
   "#"
   "&& reload_completed"
@@ -14,14 +14,21 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn "*movqi<cczn>"
-  [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m")
-       (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))
+  [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m")
+       (match_operand:QI 1 "general_operand_src" " I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,n,m,r"))
    (clobber (reg:CC CC_REG))]
   "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])"
   "@
    sub.b       %X0,%X0
    mov.b       %R1,%X0
    mov.b       %X1,%R0
+   mov.b       %X1,%R0
+   mov.b       %X1,%R0
+   mov.b       %X1,%R0
+   mov.b       %X1,%R0
+   mov.b       %X1,%R0
+   mov.b       %X1,%R0
+   mov.b       %X1,%R0
    mov.b       %R1,%X0
    mov.b       %R1,%X0
    mov.b       %X1,%R0"
@@ -88,8 +95,8 @@
 ;; movhi
 
 (define_insn_and_split "*movhi"
-  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
-       (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))]
+  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m")
+       (match_operand:HI 1 "general_operand_src" "I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,i,m,r"))]
   "!TARGET_H8300SX
     && h8300_move_ok (operands[0], operands[1])"
   "#"
@@ -98,8 +105,8 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn "*movhi<cczn>"
-  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m")
-       (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))
+  [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m")
+       (match_operand:HI 1 "general_operand_src" "I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,i,m,r"))
    (clobber (reg:CC CC_REG))]
   "!TARGET_H8300SX
     && h8300_move_ok (operands[0], operands[1])"
@@ -109,6 +116,13 @@
    mov.w       %T1,%T0
    mov.w       %T1,%T0
    mov.w       %T1,%T0
+   mov.w       %T1,%T0
+   mov.w       %T1,%T0
+   mov.w       %T1,%T0
+   mov.w       %T1,%T0
+   mov.w       %T1,%T0
+   mov.w       %T1,%T0
+   mov.w       %T1,%T0
    mov.w       %T1,%T0"
   [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))])
 
@@ -158,8 +172,8 @@
 
 ;; movsi
 (define_insn_and_split "*movsi"
-  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r")
-       (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))]
+  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m,*a,*a,r")
+       (match_operand:SI 1 "general_operand_src" "I,r,i,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>,m,r,I,r,*a"))]
   "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
     && h8300_move_ok (operands[0], operands[1])"
   "#"
@@ -168,8 +182,8 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn "*movsi_clobber_flags"
-  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a, r")
-       (match_operand:SI 1 "general_operand_src" " I,r,i,r,>,m,r, I, r,*a"))
+  [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m,*a,*a, r")
+       (match_operand:SI 1 "general_operand_src" " I,r,i,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>,m,r, I, r,*a"))
    (clobber (reg:CC CC_REG))]
   "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
     && h8300_move_ok (operands[0], operands[1])"
@@ -178,11 +192,11 @@
     {
     case 0:
       return "sub.l    %S0,%S0";
-    case 7:
+    case 14:
       return "clrmac";
-    case 8:
+    case 15:
       return "clrmac\;ldmac %1,macl";
-    case 9:
+    case 16:
       return "stmac    macl,%0";
     default:
       if (GET_CODE (operands[1]) == CONST_INT)
@@ -238,9 +252,9 @@
 (define_insn "*movsi_cczn"
   [(set (reg:CCZN CC_REG)
        (compare:CCZN
-         (match_operand:SI 1 "general_operand_src" " I,r,i,r,>,m,r")
+         (match_operand:SI 1 "general_operand_src" " I,r,i,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>,m,r")
          (const_int 0)))
-   (set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m")
+   (set (match_operand:SI 0 "general_operand_dst" "=r,r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m")
        (match_dup 1))]
   "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX
     && h8300_move_ok (operands[0], operands[1])"
@@ -251,6 +265,13 @@
    mov.l       %S1,%S0
    mov.l       %S1,%S0
    mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
    mov.l       %S1,%S0"
   [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))])
 
@@ -316,8 +337,8 @@
    (set_attr "length_table" "*,movl")])
 
 (define_insn_and_split "*movsf"
-  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
-       (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))]
+  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r")
+       (match_operand:SF 1 "general_operand_src" "G,r,im,r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>"))]
   "!TARGET_H8300SX
     && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode))"
@@ -327,8 +348,8 @@
              (clobber (reg:CC CC_REG))])])
 
 (define_insn "*movsf_clobber_flags"
-  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r")
-       (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))
+  [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r")
+       (match_operand:SF 1 "general_operand_src" "G,r,im,r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>"))
    (clobber (reg:CC CC_REG))]
   "!TARGET_H8300SX
     && (register_operand (operands[0], SFmode)
@@ -339,6 +360,13 @@
    mov.l       %S1,%S0
    mov.l       %S1,%S0
    mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
+   mov.l       %S1,%S0
    mov.l       %S1,%S0"
   [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))])
 \f