net/mlx5: Add IFC bits to support RSS for IPSec offload

This adds the capabilities, ipsec_next_header and inner/outer
l4_type_ext fields to support RSS for the decrypted packets.

These fields are specifically for firmware steering. HWS validation
logic is updated to correctly handle the changes, ensuring the
unsupported fields are not set.

Besides, reserved_at_c4 is fixed to reserved_at_d4 to reflect the
accurate offset within the structure.

Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Reviewed-by: Carolina Jubran <cjubran@nvidia.com>
Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://patch.msgid.link/1752734895-257735-2-git-send-email-tariqt@nvidia.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
index d45e1145d1979ac58c2a780c63d24ff5348a6b56..c6436c3a7a8306f0174bd810444aec872910ce56 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c
@@ -727,8 +727,9 @@ hws_definer_conv_outer(struct mlx5hws_definer_conv_data *cd,
        u32 *s_ipv6, *d_ipv6;
 
        if (HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type, 0x2) ||
-           HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c2, 0xe) ||
-           HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c4, 0x4)) {
+           HWS_IS_FLD_SET_SZ(match_param, outer_headers.l4_type_ext, 0x4) ||
+           HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_c6, 0xa) ||
+           HWS_IS_FLD_SET_SZ(match_param, outer_headers.reserved_at_d4, 0x4)) {
                mlx5hws_err(cd->ctx, "Unsupported outer parameters set\n");
                return -EINVAL;
        }
@@ -903,8 +904,9 @@ hws_definer_conv_inner(struct mlx5hws_definer_conv_data *cd,
        u32 *s_ipv6, *d_ipv6;
 
        if (HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type, 0x2) ||
-           HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c2, 0xe) ||
-           HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c4, 0x4)) {
+           HWS_IS_FLD_SET_SZ(match_param, inner_headers.l4_type_ext, 0x4) ||
+           HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_c6, 0xa) ||
+           HWS_IS_FLD_SET_SZ(match_param, inner_headers.reserved_at_d4, 0x4)) {
                mlx5hws_err(cd->ctx, "Unsupported inner parameters set\n");
                return -EINVAL;
        }
@@ -1279,7 +1281,8 @@ hws_definer_conv_misc2(struct mlx5hws_definer_conv_data *cd,
        struct mlx5hws_definer_fc *curr_fc;
 
        if (HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1a0, 0x8) ||
-           HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1b8, 0x8) ||
+           HWS_IS_FLD_SET_SZ(match_param,
+                             misc_parameters_2.ipsec_next_header, 0x8) ||
            HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1c0, 0x40) ||
            HWS_IS_FLD_SET(match_param, misc_parameters_2.macsec_syndrome) ||
            HWS_IS_FLD_SET(match_param, misc_parameters_2.ipsec_syndrome)) {

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 639dd0b56655be7269cfc19c77b6a0902a4d3366..c9a7773ac8ecac5ae2d9c927c25052d5f952e0c6 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -420,7 +420,8 @@ struct mlx5_ifc_flow_table_fields_supported_bits {
 
 /* Table 2170 - Flow Table Fields Supported 2 Format */
 struct mlx5_ifc_flow_table_fields_supported_2_bits {
-       u8         reserved_at_0[0x2];
+       u8         inner_l4_type_ext[0x1];
+       u8         outer_l4_type_ext[0x1];
        u8         inner_l4_type[0x1];
        u8         outer_l4_type[0x1];
        u8         reserved_at_4[0xa];
@@ -429,7 +430,11 @@ struct mlx5_ifc_flow_table_fields_supported_2_bits {
        u8         tunnel_header_0_1[0x1];
        u8         reserved_at_11[0xf];
 
-       u8         reserved_at_20[0x60];
+       u8         reserved_at_20[0xf];
+       u8         ipsec_next_header[0x1];
+       u8         reserved_at_30[0x10];
+
+       u8         reserved_at_40[0x40];
 };
 
 struct mlx5_ifc_flow_table_prop_layout_bits {
@@ -552,6 +557,13 @@ enum {
        MLX5_PACKET_L4_TYPE_UDP,
 };
 
+enum {
+       MLX5_PACKET_L4_TYPE_EXT_NONE,
+       MLX5_PACKET_L4_TYPE_EXT_TCP,
+       MLX5_PACKET_L4_TYPE_EXT_UDP,
+       MLX5_PACKET_L4_TYPE_EXT_ICMP,
+};
+
 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
        u8         smac_47_16[0x20];
 
@@ -578,10 +590,10 @@ struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
        u8         tcp_dport[0x10];
 
        u8         l4_type[0x2];
-       u8         reserved_at_c2[0xe];
+       u8         l4_type_ext[0x4];
+       u8         reserved_at_c6[0xa];
        u8         ipv4_ihl[0x4];
-       u8         reserved_at_c4[0x4];
-
+       u8         reserved_at_d4[0x4];
        u8         ttl_hoplimit[0x8];
 
        u8         udp_sport[0x10];
@@ -689,10 +701,9 @@ struct mlx5_ifc_fte_match_set_misc2_bits {
        u8         metadata_reg_a[0x20];
 
        u8         reserved_at_1a0[0x8];
-
        u8         macsec_syndrome[0x8];
        u8         ipsec_syndrome[0x8];
-       u8         reserved_at_1b8[0x8];
+       u8         ipsec_next_header[0x8];
 
        u8         reserved_at_1c0[0x40];
 };