net: stmmac: qcom-ethqos: finally eliminate the switch

Move the RCLK delay configuration out of the switch, which just leaves
the RGMII_CONFIG_LOOPBACK_EN setting in all three paths. This makes it
trivial to eliminate the switch.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>
Link: https://patch.msgid.link/E1w62nj-0000000E3Cq-1lPL@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index b4c61cb24e1d9e22252414877f98c7a7f76d820f..7690ae0bb00816cf779da668f572772d42a40975 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -444,8 +444,18 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                rgmii_clrmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
                              RGMII_IO_MACRO_CONFIG2);
 
-       switch (speed) {
-       case SPEED_1000:
+       if (speed != SPEED_1000) {
+               /* Write 0x5 to PRG_RCLK_DLY_CODE */
+               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+                             FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
+                                        5), SDCC_HC_REG_DDR_CONFIG);
+
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
+                             SDCC_HC_REG_DDR_CONFIG);
+
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+                             SDCC_HC_REG_DDR_CONFIG);
+       } else {
                /* PRG_RCLK_DLY = TCXO period * TCXO_CYCLES_CNT / 2 * RX delay ns,
                 * in practice this becomes PRG_RCLK_DLY = 52 * 4 / 2 * RX delay ns
                 */
@@ -460,39 +470,14 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
                                      FIELD_PREP(SDCC_DDR_CONFIG_PRG_RCLK_DLY,
                                                 57), SDCC_HC_REG_DDR_CONFIG);
                }
-               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
-                             SDCC_HC_REG_DDR_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
-                             loopback, RGMII_IO_MACRO_CONFIG);
-               break;
-
-       case SPEED_100:
-               /* Write 0x5 to PRG_RCLK_DLY_CODE */
-               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
-                             FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
-                                        5), SDCC_HC_REG_DDR_CONFIG);
-               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
-                             SDCC_HC_REG_DDR_CONFIG);
-               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
-                             SDCC_HC_REG_DDR_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
-                             loopback, RGMII_IO_MACRO_CONFIG);
-               break;
 
-       case SPEED_10:
-               /* Write 0x5 to PRG_RCLK_DLY_CODE */
-               rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
-                             FIELD_PREP(SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
-                                        5), SDCC_HC_REG_DDR_CONFIG);
-               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
-                             SDCC_HC_REG_DDR_CONFIG);
-               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
+               rgmii_setmask(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
                              SDCC_HC_REG_DDR_CONFIG);
-               rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
-                             loopback, RGMII_IO_MACRO_CONFIG);
-               break;
        }
 
+       rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN, loopback,
+                     RGMII_IO_MACRO_CONFIG);
+
        return 0;
 }