pinctrl: mediatek: mt8167: Fix Schmitt trigger register offset of pins 34-39

The correct Schmitt trigger register offset for pins 34-39 is 0xA00. Value
was verified with SoC data sheet.

Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Fixes: 82d70627e94a ("pinctrl: mediatek: Add MT8167 Pinctrl driver")
Signed-off-by: Linus Walleij <linusw@kernel.org>

diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
index 143c2662227252519a14954fb9e801eacb31eb07..c812d614e9d453869e8f6dee576fd4cd7ef79f36 100644 (file)
--- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c
@@ -244,7 +244,7 @@ static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
        MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
        MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
        MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
-       MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
+       MTK_PIN_IES_SMT_SPEC(34, 39, 0xA00, 2),
        MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
        MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
        MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),