RISC-V: Allow any temp register to be used in amo tests

We artifically restrict the temp registers to be a[0-9]+ when other
registers like t[0-9]+ are valid too. Update to make the regex
accept any register for the temp value.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/amo/amo-table-a-6-load-1.c: Update temp register regex.
	* gcc.target/riscv/amo/amo-table-a-6-load-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-load-3.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-store-1.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-store-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-load-1.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-load-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-load-3.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-store-1.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-store-2.c: Ditto.
	* gcc.target/riscv/amo/amo-table-ztso-store-3.c: Ditto.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
index 3c79035e46d682f302d47ad7e1442dc7233dc399..53dd523445273da4ed456b5cfce788ef119b8295 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-1.c
@@ -6,8 +6,8 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a0\)
-**     sw\ta[0-9]+,0\(a1\)
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
index 7d74841846fac5f4476a1ef1e41236c3b49a6b89..dda0f541515653af40a05f3e54ef11b6411191ce 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-2.c
@@ -6,9 +6,9 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a0\)
+**     lw\t[atx][0-9]+,0\(a0\)
 **     fence\tr,rw
-**     sw\ta[0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a1\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
index ab95fa660d2523fc35d375d6f5fbc6b0869fb0ec..3279557fa4a92e05553cabf1507efe09adb199ce 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-load-3.c
@@ -7,9 +7,9 @@
 /*
 ** foo:
 **     fence\trw,rw
-**     lw\ta[0-9]+,0\(a0\)
+**     lw\t[atx][0-9]+,0\(a0\)
 **     fence\tr,rw
-**     sw\ta[0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a1\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
index d852fddf03de532d662b82a7cbff4377ef80aa43..6b05429520bf6a00a51fe1473db203bcc5d3f0aa 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-1.c
@@ -6,8 +6,8 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a1\)
-**     sw\ta[0-9]+,0\(a0\)
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
index ccb5e2af7cc16244f432dc7d6e02a0d37805d2bd..1ad7dede931bd965dce63ac8a56cb4806a081e3e 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-2.c
@@ -6,9 +6,9 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a1\)
+**     lw\t[atx][0-9]+,0\(a1\)
 **     fence\trw,w
-**     sw\ta[0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c
index 761889f18cf9dbe732da4dbdcddabee6403b23c8..b16b2058413a3704f2cdd5925de64cad51444319 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-a-6-store-compat-3.c
@@ -6,9 +6,9 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a1\)
+**     lw\t[atx][0-9]+,0\(a1\)
 **     fence\trw,w
-**     sw\ta[0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a0\)
 **     fence\trw,rw
 **     ret
 */

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c
index 631977985bd5309c21c563d82638f09c363750be..ebb0a2e1d38e7e81b1701946bbe881eca4f0459d 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-1.c
@@ -7,8 +7,8 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a0\)
-**     sw\ta[0-9]+,0\(a1\)
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c
index 2c24f10fb44dc6a94f622f24c9e88df6bbfe8174..c88c4be5aea62bfeab73a422c4dd581d5ce26419 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-2.c
@@ -7,8 +7,8 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a0\)
-**     sw\ta[0-9]+,0\(a1\)
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c
index 7d2166d29c050a950055ac3a86e3735815e869fa..8713729c378b8da2807659723a597f13b8bfa6b8 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-load-3.c
@@ -8,8 +8,8 @@
 /*
 ** foo:
 **     fence\trw,rw
-**     lw\ta[0-9]+,0\(a0\)
-**     sw\ta[0-9]+,0\(a1\)
+**     lw\t[atx][0-9]+,0\(a0\)
+**     sw\t[atx][0-9]+,0\(a1\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c
index 29a770285ef6df64779f62495cd1e59d144c6d7b..ca8d5ed7515daf433e880544d2a33748d99f4296 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-1.c
@@ -7,8 +7,8 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a1\)
-**     sw\ta[0-9]+,0\(a0\)
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c
index fb82360ad336f18db1cf53e379db5bbf168a0514..23957198cfbd2d01704439198ce00b5a9d647e51 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-2.c
@@ -7,8 +7,8 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a1\)
-**     sw\ta[0-9]+,0\(a0\)
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
 **     ret
 */
 void foo (int* bar, int* baz)

diff --git a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c
index 88d8432d8c9bf4c3212249539685af514116fb4a..11c12f0ca1ad14a1615680e32461fee0385d01fb 100644 (file)
--- a/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c
+++ b/gcc/testsuite/gcc.target/riscv/amo/amo-table-ztso-store-3.c
@@ -7,8 +7,8 @@
 
 /*
 ** foo:
-**     lw\ta[0-9]+,0\(a1\)
-**     sw\ta[0-9]+,0\(a0\)
+**     lw\t[atx][0-9]+,0\(a1\)
+**     sw\t[atx][0-9]+,0\(a0\)
 **     fence\trw,rw
 **     ret
 */