LoongArch: Fix incorrect reorder of __lsx_vldx and __lasx_xvldx [PR119084]

They could be incorrectly reordered with store instructions like st.b
because the RTL expression does not have a memory_operand or a (mem)
expression.  The incorrect reorder has been observed in openh264 LTO
build.

Expand them to a (mem) expression instead of unspec to fix the issue.

Closes: https://github.com/cisco/openh264/issues/3857
(cherry picked from commit 4856292f7a680ec478e7607f1b71781996d7d542)

Edited to remove the loongarch.cc change which is not needed for gcc-14
branch.

gcc/ChangeLog:

	PR target/119084
	* config/loongarch/lasx.md (UNSPEC_LASX_XVLDX): Remove.
	(lasx_xvldx): Remove.
	* config/loongarch/lsx.md (UNSPEC_LSX_VLDX): Remove.
	(lsx_vldx): Remove.
	* config/loongarch/simd.md (QIVEC): New define_mode_iterator.
	(<simd_isa>_<x>vldx): New define_expand.

gcc/testsuite/ChangeLog:

	PR target/119084
	* gcc.target/loongarch/pr119084.c: New test.

diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md
index 94bbd0c26bbc4a23f0d91c3d8af02c97507e226c..fe32194e8119dbbe070d3660297cb87f40a8d310 100644 (file)
--- a/gcc/config/loongarch/lasx.md
+++ b/gcc/config/loongarch/lasx.md
@@ -155,7 +155,6 @@
   UNSPEC_LASX_XVSSRLRN
   UNSPEC_LASX_XVEXTL_QU_DU
   UNSPEC_LASX_XVLDI
-  UNSPEC_LASX_XVLDX
   UNSPEC_LASX_XVSTX
   UNSPEC_LASX_VECINIT_MERGE
   UNSPEC_LASX_VEC_SET_INTERNAL
@@ -4679,18 +4678,6 @@
   [(set_attr "type" "simd_load")
    (set_attr "mode" "V4DI")])
 
-(define_insn "lasx_xvldx"
-  [(set (match_operand:V32QI 0 "register_operand" "=f")
-       (unspec:V32QI [(match_operand:DI 1 "register_operand" "r")
-                      (match_operand:DI 2 "reg_or_0_operand" "rJ")]
-                     UNSPEC_LASX_XVLDX))]
-  "ISA_HAS_LASX"
-{
-  return "xvldx\t%u0,%1,%z2";
-}
-  [(set_attr "type" "simd_load")
-   (set_attr "mode" "V32QI")])
-
 (define_insn "lasx_xvstx"
   [(set (mem:V32QI (plus:DI (match_operand:DI 1 "register_operand" "r")
                            (match_operand:DI 2 "reg_or_0_operand" "rJ")))

diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md
index 5ee5845e84b017605027fbf7813a11ff1e5855f0..67ba8e8ad5d7519df6a174250b13dc2001298608 100644 (file)
--- a/gcc/config/loongarch/lsx.md
+++ b/gcc/config/loongarch/lsx.md
@@ -100,7 +100,6 @@
   UNSPEC_LSX_VSSRLRN
   UNSPEC_LSX_VLDI
   UNSPEC_LSX_VSHUF_B
-  UNSPEC_LSX_VLDX
   UNSPEC_LSX_VSTX
   UNSPEC_LSX_VEXTL_QU_DU
   UNSPEC_LSX_VSETEQZ_V
@@ -3070,18 +3069,6 @@
   [(set_attr "type" "simd_shf")
    (set_attr "mode" "V16QI")])
 
-(define_insn "lsx_vldx"
-  [(set (match_operand:V16QI 0 "register_operand" "=f")
-       (unspec:V16QI [(match_operand:DI 1 "register_operand" "r")
-                      (match_operand:DI 2 "reg_or_0_operand" "rJ")]
-                     UNSPEC_LSX_VLDX))]
-  "ISA_HAS_LSX"
-{
-  return "vldx\t%w0,%1,%z2";
-}
-  [(set_attr "type" "simd_load")
-   (set_attr "mode" "V16QI")])
-
 (define_insn "lsx_vstx"
   [(set (mem:V16QI (plus:DI (match_operand:DI 1 "register_operand" "r")
                            (match_operand:DI 2 "reg_or_0_operand" "rJ")))

diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md
index 00ff2823a4e2f0c4b32b7b0e16bd9136f246b8a0..691e719563626def42fbfa03bb24f54906ddf093 100644 (file)
--- a/gcc/config/loongarch/simd.md
+++ b/gcc/config/loongarch/simd.md
@@ -113,6 +113,16 @@
 ;; instruction here so we can avoid duplicating logics.
 ;; =======================================================================
 
+;; REG + REG load
+
+(define_mode_iterator QIVEC [(V16QI "ISA_HAS_LSX") (V32QI "ISA_HAS_LASX")])
+(define_expand "<simd_isa>_<x>vldx"
+  [(set (match_operand:QIVEC 0 "register_operand" "=f")
+       (mem:QIVEC (plus:DI (match_operand:DI 1 "register_operand")
+                           (match_operand:DI 2 "register_operand"))))]
+  "TARGET_64BIT")
+
+
 ;;
 ;; FP vector rounding instructions
 ;;

diff --git a/gcc/testsuite/gcc.target/loongarch/pr119084.c b/gcc/testsuite/gcc.target/loongarch/pr119084.c
new file mode 100644 (file)
index 0000000..b594330
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/pr119084.c
@@ -0,0 +1,24 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mlsx" } */
+/* { dg-require-effective-target loongarch_sx_hw } */
+
+typedef signed char V16QI __attribute__ ((vector_size (16)));
+static char x[128];
+
+__attribute__ ((noipa)) int
+noopt (int x)
+{
+  return x;
+}
+
+int
+main (void)
+{
+  int t = noopt (32);
+
+  x[32] = 1;
+
+  V16QI y = __builtin_lsx_vldx (x, t);
+  if (y[0] != 1)
+    __builtin_trap ();
+}