#define MMC_RXVLANFRAMES_GB_LO 0x0998
#define MMC_RXVLANFRAMES_GB_HI 0x099c
#define MMC_RXWATCHDOGERROR 0x09a0
+#define MMC_RXALIGNMENTERROR 0x09bc
/* MMC register entry bit positions and sizes */
#define MMC_CR_CR_INDEX 0
#define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
#define MMC_RISR_RXWATCHDOGERROR_INDEX 22
#define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
+#define MMC_RISR_RXALIGNMENTERROR_INDEX 27
+#define MMC_RISR_RXALIGNMENTERROR_WIDTH 1
#define MMC_TIER_ALL_INTERRUPTS_INDEX 0
#define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
#define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
case MMC_RXUNDERSIZE_G:
case MMC_RXOVERSIZE_G:
case MMC_RXWATCHDOGERROR:
+ case MMC_RXALIGNMENTERROR:
read_hi = false;
break;
if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
stats->rxwatchdogerror +=
xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
+
+ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXALIGNMENTERROR))
+ stats->rxalignmenterror +=
+ xgbe_mmc_read(pdata, MMC_RXALIGNMENTERROR);
}
static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
stats->rxwatchdogerror +=
xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
+ stats->rxalignmenterror +=
+ xgbe_mmc_read(pdata, MMC_RXALIGNMENTERROR);
+
/* Un-freeze counters */
XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
}
s->rx_length_errors = pstats->rxlengtherror;
s->rx_crc_errors = pstats->rxcrcerror;
s->rx_over_errors = pstats->rxfifooverflow;
+ s->rx_frame_errors = pstats->rxalignmenterror;
s->tx_packets = pstats->txframecount_gb;
s->tx_bytes = pstats->txoctetcount_gb;