]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
scsi: ufs: ufs-pci: Fix hibernate state transition for Intel MTL-like host controllers
authorArchana Patni <archana.patni@intel.com>
Wed, 23 Jul 2025 16:58:49 +0000 (19:58 +0300)
committerMartin K. Petersen <martin.petersen@oracle.com>
Fri, 25 Jul 2025 02:37:29 +0000 (22:37 -0400)
UFSHCD core disables the UIC completion interrupt when issuing UIC
hibernation commands, and re-enables it afterwards if it was enabled to
start with, refer ufshcd_uic_pwr_ctrl(). For Intel MTL-like host
controllers, accessing the register to re-enable the interrupt disrupts
the state transition.

Use hibern8_notify variant operation to disable the interrupt during the
entire hibernation, thereby preventing the disruption.

Fixes: 4049f7acef3e ("scsi: ufs: ufs-pci: Add support for Intel MTL")
Cc: stable@vger.kernel.org
Signed-off-by: Archana Patni <archana.patni@intel.com>
Link: https://lore.kernel.org/r/20250723165856.145750-2-adrian.hunter@intel.com
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
drivers/ufs/host/ufshcd-pci.c

index 996387906aa14ecb30673668bb4b4e6dd0d12b25..af1c272eef1c1b5babb7570200ca1aae27506459 100644 (file)
@@ -216,6 +216,32 @@ out:
        return ret;
 }
 
+static void ufs_intel_ctrl_uic_compl(struct ufs_hba *hba, bool enable)
+{
+       u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
+
+       if (enable)
+               set |= UIC_COMMAND_COMPL;
+       else
+               set &= ~UIC_COMMAND_COMPL;
+       ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
+}
+
+static void ufs_intel_mtl_h8_notify(struct ufs_hba *hba,
+                                   enum uic_cmd_dme cmd,
+                                   enum ufs_notify_change_status status)
+{
+       /*
+        * Disable UIC COMPL INTR to prevent access to UFSHCI after
+        * checking HCS.UPMCRS
+        */
+       if (status == PRE_CHANGE && cmd == UIC_CMD_DME_HIBER_ENTER)
+               ufs_intel_ctrl_uic_compl(hba, false);
+
+       if (status == POST_CHANGE && cmd == UIC_CMD_DME_HIBER_EXIT)
+               ufs_intel_ctrl_uic_compl(hba, true);
+}
+
 #define INTEL_ACTIVELTR                0x804
 #define INTEL_IDLELTR          0x808
 
@@ -533,6 +559,7 @@ static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = {
        .init                   = ufs_intel_mtl_init,
        .exit                   = ufs_intel_common_exit,
        .hce_enable_notify      = ufs_intel_hce_enable_notify,
+       .hibern8_notify         = ufs_intel_mtl_h8_notify,
        .link_startup_notify    = ufs_intel_link_startup_notify,
        .resume                 = ufs_intel_resume,
        .device_reset           = ufs_intel_device_reset,