#define _MAKE_ALT_CHAN(ch) (ch | (IPU_MAX_CH << 24))
#define IPU_CHAN_ID(ch) (ch >> 24)
#define IPU_CHAN_ALT(ch) (ch & 0x02000000)
-#define IPU_CHAN_ALPHA_IN_DMA(ch) ((uint32_t)(ch >> 6) & 0x3F)
-#define IPU_CHAN_GRAPH_IN_DMA(ch) ((uint32_t)(ch >> 12) & 0x3F)
-#define IPU_CHAN_VIDEO_IN_DMA(ch) ((uint32_t)(ch >> 18) & 0x3F)
-#define IPU_CHAN_OUT_DMA(ch) ((uint32_t)(ch & 0x3F))
+#define IPU_CHAN_ALPHA_IN_DMA(ch) ((u32)(ch >> 6) & 0x3F)
+#define IPU_CHAN_GRAPH_IN_DMA(ch) ((u32)(ch >> 12) & 0x3F)
+#define IPU_CHAN_VIDEO_IN_DMA(ch) ((u32)(ch >> 18) & 0x3F)
+#define IPU_CHAN_OUT_DMA(ch) ((u32)(ch & 0x3F))
#define NO_DMA 0x3F
#define ALT 1
*/
typedef union {
struct {
- uint32_t di;
+ u32 di;
unsigned char interlaced;
} mem_dc_sync;
struct {
- uint32_t temp;
+ u32 temp;
} mem_sdc_fg;
struct {
- uint32_t di;
+ u32 di;
unsigned char interlaced;
- uint32_t in_pixel_fmt;
- uint32_t out_pixel_fmt;
+ u32 in_pixel_fmt;
+ u32 out_pixel_fmt;
unsigned char alpha_chan_en;
} mem_dp_bg_sync;
struct {
- uint32_t temp;
+ u32 temp;
} mem_sdc_bg;
struct {
- uint32_t di;
+ u32 di;
unsigned char interlaced;
- uint32_t in_pixel_fmt;
- uint32_t out_pixel_fmt;
+ u32 in_pixel_fmt;
+ u32 out_pixel_fmt;
unsigned char alpha_chan_en;
} mem_dp_fg_sync;
} ipu_channel_params_t;
void ipu_uninit_channel(ipu_channel_t channel);
int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
- uint32_t pixel_fmt, uint16_t width,
- uint16_t height, uint32_t stride,
- dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
- uint32_t u_offset, uint32_t v_offset);
+ u32 pixel_fmt, u16 width, u16 height,
+ u32 stride, dma_addr_t phyaddr_0,
+ dma_addr_t phyaddr_1, u32 u_offset,
+ u32 v_offset);
void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
- uint32_t bufNum);
+ u32 bufNum);
int32_t ipu_enable_channel(ipu_channel_t channel);
int32_t ipu_disable_channel(ipu_channel_t channel);
-int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, uint16_t width,
- uint16_t height, uint32_t pixel_fmt,
- uint16_t h_start_width, uint16_t h_sync_width,
- uint16_t h_end_width, uint16_t v_start_width,
- uint16_t v_sync_width, uint16_t v_end_width,
- uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig);
+int32_t ipu_init_sync_panel(int disp, u32 pixel_clk, u16 width, u16 height,
+ u32 pixel_fmt, u16 h_start_width, u16 h_sync_width,
+ u16 h_end_width, u16 v_start_width,
+ u16 v_sync_width, u16 v_end_width, u32 v_to_h_sync,
+ ipu_di_signal_cfg_t sig);
int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
- uint8_t alpha);
+ u8 alpha);
int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
- uint32_t colorKey);
+ u32 colorKey);
-uint32_t bytes_per_pixel(uint32_t fmt);
+u32 bytes_per_pixel(u32 fmt);
void clk_enable(struct clk *clk);
void clk_disable(struct clk *clk);
void ipu_dc_init(int dc_chan, int di, unsigned char interlaced);
void ipu_dc_uninit(int dc_chan);
void ipu_dp_dc_enable(ipu_channel_t channel);
-int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
- uint32_t out_pixel_fmt);
+int ipu_dp_init(ipu_channel_t channel, u32 in_pixel_fmt, u32 out_pixel_fmt);
void ipu_dp_uninit(ipu_channel_t channel);
void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap);
-ipu_color_space_t format_to_colorspace(uint32_t fmt);
+ipu_color_space_t format_to_colorspace(u32 fmt);
#endif
extern u32 *ipu_cpmem_base;
struct ipu_ch_param_word {
- uint32_t data[5];
- uint32_t res[3];
+ u32 data[5];
+ u32 res[3];
};
struct ipu_ch_param {
struct clk *g_di_clk[2];
struct clk *g_pixel_clk[2];
unsigned char g_dc_di_assignment[10];
-uint32_t g_channel_init_mask;
-uint32_t g_channel_enable_mask;
+u32 g_channel_init_mask;
+u32 g_channel_enable_mask;
static int ipu_dc_use_count;
static int ipu_dp_use_count;
/* Static functions */
-static inline void ipu_ch_param_set_high_priority(uint32_t ch)
+static inline void ipu_ch_param_set_high_priority(u32 ch)
{
ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 93, 2, 1);
};
-static inline uint32_t channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
+static inline u32 channel_2_dma(ipu_channel_t ch, ipu_buffer_t type)
{
- return ((uint32_t)ch >> (6 * type)) & 0x3F;
+ return ((u32)ch >> (6 * type)) & 0x3F;
};
/* Either DP BG or DP FG can be graphic window */
-static inline int ipu_is_dp_graphic_chan(uint32_t dma_chan)
+static inline int ipu_is_dp_graphic_chan(u32 dma_chan)
{
return (dma_chan == 23 || dma_chan == 27);
}
-static inline int ipu_is_dmfc_chan(uint32_t dma_chan)
+static inline int ipu_is_dmfc_chan(u32 dma_chan)
{
return ((dma_chan >= 23) && (dma_chan <= 29));
}
-static inline void ipu_ch_param_set_buffer(uint32_t ch, int bufNum,
+static inline void ipu_ch_param_set_buffer(u32 ch, int bufNum,
dma_addr_t phyaddr)
{
ipu_ch_param_mod_field(ipu_ch_param_addr(ch), 1, 29 * bufNum, 29,
int32_t ipu_init_channel(ipu_channel_t channel, ipu_channel_params_t *params)
{
int ret = 0;
- uint32_t ipu_conf;
+ u32 ipu_conf;
debug("init channel = %d\n", IPU_CHAN_ID(channel));
*/
void ipu_uninit_channel(ipu_channel_t channel)
{
- uint32_t reg;
- uint32_t in_dma, out_dma = 0;
- uint32_t ipu_conf;
+ u32 reg;
+ u32 in_dma, out_dma = 0;
+ u32 ipu_conf;
if ((g_channel_init_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
debug("Channel already uninitialized %d\n",
ipu_ch_param_set_field(p, 1, 143, 5, alpha_offset);
}
-static void ipu_ch_param_init(int ch, uint32_t pixel_fmt, uint32_t width,
- uint32_t height, uint32_t stride, uint32_t u,
- uint32_t v, uint32_t uv_stride, dma_addr_t addr0,
- dma_addr_t addr1)
+static void ipu_ch_param_init(int ch, u32 pixel_fmt, u32 width, u32 height,
+ u32 stride, u32 u, u32 v, u32 uv_stride,
+ dma_addr_t addr0, dma_addr_t addr1)
{
- uint32_t u_offset = 0;
- uint32_t v_offset = 0;
+ u32 u_offset = 0;
+ u32 v_offset = 0;
struct ipu_ch_param params;
memset(¶ms, 0, sizeof(params));
* Return: Returns 0 on success or negative error code on fail
*/
int32_t ipu_init_channel_buffer(ipu_channel_t channel, ipu_buffer_t type,
- uint32_t pixel_fmt, uint16_t width,
- uint16_t height, uint32_t stride,
- dma_addr_t phyaddr_0, dma_addr_t phyaddr_1,
- uint32_t u, uint32_t v)
+ u32 pixel_fmt, u16 width, u16 height,
+ u32 stride, dma_addr_t phyaddr_0,
+ dma_addr_t phyaddr_1, u32 u, u32 v)
{
- uint32_t reg;
- uint32_t dma_chan;
+ u32 reg;
+ u32 dma_chan;
dma_chan = channel_2_dma(channel, type);
if (!idma_is_valid(dma_chan))
*/
int32_t ipu_enable_channel(ipu_channel_t channel)
{
- uint32_t reg;
- uint32_t in_dma;
- uint32_t out_dma;
+ u32 reg;
+ u32 in_dma;
+ u32 out_dma;
if (g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) {
printf("Warning: channel already enabled %d\n",
*
*/
void ipu_clear_buffer_ready(ipu_channel_t channel, ipu_buffer_t type,
- uint32_t bufNum)
+ u32 bufNum)
{
- uint32_t dma_ch = channel_2_dma(channel, type);
+ u32 dma_ch = channel_2_dma(channel, type);
if (!idma_is_valid(dma_ch))
return;
*/
int32_t ipu_disable_channel(ipu_channel_t channel)
{
- uint32_t reg;
- uint32_t in_dma;
- uint32_t out_dma;
+ u32 reg;
+ u32 in_dma;
+ u32 out_dma;
if ((g_channel_enable_mask & (1L << IPU_CHAN_ID(channel))) == 0) {
debug("Channel already disabled %d\n", IPU_CHAN_ID(channel));
return 0;
}
-uint32_t bytes_per_pixel(uint32_t fmt)
+u32 bytes_per_pixel(u32 fmt)
{
switch (fmt) {
case IPU_PIX_FMT_GENERIC: /*generic data */
return 0;
}
-ipu_color_space_t format_to_colorspace(uint32_t fmt)
+ipu_color_space_t format_to_colorspace(u32 fmt)
{
switch (fmt) {
case IPU_PIX_FMT_RGB666:
}
}
-int ipu_dp_init(ipu_channel_t channel, uint32_t in_pixel_fmt,
- uint32_t out_pixel_fmt)
+int ipu_dp_init(ipu_channel_t channel, u32 in_pixel_fmt, u32 out_pixel_fmt)
{
int in_fmt, out_fmt;
int dp;
int partial = 0;
- uint32_t reg;
+ u32 reg;
if (channel == MEM_FG_SYNC) {
dp = DP_SYNC;
((fg_csc_type == YUV2RGB) && (bg_csc_type == YUV2RGB)))) {
int red, green, blue;
int y, u, v;
- uint32_t color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) &
- 0xFFFFFFL;
+ u32 color_key = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0xFFFFFFL;
debug("_ipu_dp_init color key 0x%x need change to yuv fmt!\n",
color_key);
void ipu_dp_dc_enable(ipu_channel_t channel)
{
int di;
- uint32_t reg;
- uint32_t dc_chan;
+ u32 reg;
+ u32 dc_chan;
if (channel == MEM_DC_SYNC)
dc_chan = 1;
void ipu_dp_dc_disable(ipu_channel_t channel, unsigned char swap)
{
- uint32_t reg;
- uint32_t csc;
- uint32_t dc_chan = 0;
+ u32 reg;
+ u32 csc;
+ u32 dc_chan = 0;
int timeout = 50;
int irq = 0;
ipu_dc_map_config(4, 2, 21, 0xFC);
}
-static int ipu_pixfmt_to_map(uint32_t fmt)
+static int ipu_pixfmt_to_map(u32 fmt)
{
switch (fmt) {
case IPU_PIX_FMT_GENERIC:
* fail.
*/
-int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, uint16_t width,
- uint16_t height, uint32_t pixel_fmt,
- uint16_t h_start_width, uint16_t h_sync_width,
- uint16_t h_end_width, uint16_t v_start_width,
- uint16_t v_sync_width, uint16_t v_end_width,
- uint32_t v_to_h_sync, ipu_di_signal_cfg_t sig)
+int32_t ipu_init_sync_panel(int disp, u32 pixel_clk, u16 width, u16 height,
+ u32 pixel_fmt, u16 h_start_width, u16 h_sync_width,
+ u16 h_end_width, u16 v_start_width,
+ u16 v_sync_width, u16 v_end_width, u32 v_to_h_sync,
+ ipu_di_signal_cfg_t sig)
{
- uint32_t reg;
- uint32_t di_gen, vsync_cnt;
- uint32_t div, rounded_pixel_clk;
- uint32_t h_total, v_total;
+ u32 reg;
+ u32 di_gen, vsync_cnt;
+ u32 div, rounded_pixel_clk;
+ u32 h_total, v_total;
int map;
struct clk *di_parent;
* Return: Returns 0 on success or negative error code on fail
*/
int32_t ipu_disp_set_global_alpha(ipu_channel_t channel, unsigned char enable,
- uint8_t alpha)
+ u8 alpha)
{
- uint32_t reg;
+ u32 reg;
unsigned char bg_chan;
if (enable) {
reg = __raw_readl(DP_GRAPH_WIND_CTRL()) & 0x00FFFFFFL;
- __raw_writel(reg | ((uint32_t)alpha << 24),
- DP_GRAPH_WIND_CTRL());
+ __raw_writel(reg | ((u32)alpha << 24), DP_GRAPH_WIND_CTRL());
reg = __raw_readl(DP_COM_CONF());
__raw_writel(reg | DP_COM_CONF_GWAM, DP_COM_CONF());
* Return: Returns 0 on success or negative error code on fail
*/
int32_t ipu_disp_set_color_key(ipu_channel_t channel, unsigned char enable,
- uint32_t color_key)
+ u32 color_key)
{
- uint32_t reg;
+ u32 reg;
int y, u, v;
int red, green, blue;
static int mxcfb_unmap_video_memory(struct fb_info *fbi);
static struct fb_videomode const *gmode;
-static uint8_t gdisp;
-static uint32_t gpixfmt;
+static u8 gdisp;
+static u32 gpixfmt;
static void fb_videomode_to_var(struct fb_var_screeninfo *var,
const struct fb_videomode *mode)
dma_addr_t alpha_phy_addr1;
void *alpha_virt_addr0;
void *alpha_virt_addr1;
- uint32_t alpha_mem_len;
- uint32_t cur_ipu_buf;
- uint32_t cur_ipu_alpha_buf;
+ u32 alpha_mem_len;
+ u32 cur_ipu_buf;
+ u32 cur_ipu_alpha_buf;
u32 pseudo_palette[16];
};
static struct fb_info *mxcfb_info[3];
static int ext_clk_used;
-static uint32_t bpp_to_pixfmt(struct fb_info *fbi)
+static u32 bpp_to_pixfmt(struct fb_info *fbi)
{
- uint32_t pixfmt = 0;
+ u32 pixfmt = 0;
debug("bpp_to_pixfmt: %d\n", fbi->var.bits_per_pixel);
u32 mem_len;
ipu_di_signal_cfg_t sig_cfg;
struct mxcfb_info *mxc_fbi = (struct mxcfb_info *)fbi->par;
- uint32_t out_pixel_fmt;
+ u32 out_pixel_fmt;
ipu_disable_channel(mxc_fbi->ipu_ch);
ipu_uninit_channel(mxc_fbi->ipu_ch);
}
debug("allocated fb @ paddr=0x%08X, size=%d.\n",
- (uint32_t)fbi->fix.smem_start, fbi->fix.smem_len);
+ (u32)fbi->fix.smem_start, fbi->fix.smem_len);
fbi->screen_size = fbi->fix.smem_len;
*
* Return: Appropriate error code to the kernel common code
*/
-static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt, uint8_t disp,
+static int mxcfb_probe(struct udevice *dev, u32 interface_pix_fmt, u8 disp,
struct fb_videomode const *mode)
{
struct fb_info *fbi;
}
}
-int ipuv3_fb_init(struct fb_videomode const *mode, uint8_t disp,
- uint32_t pixfmt)
+int ipuv3_fb_init(struct fb_videomode const *mode, u8 disp, u32 pixfmt)
{
gmode = mode;
gdisp = disp;
projects / thirdparty / u-boot.git / commitdiff
