]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt types
authorBiju Das <biju.das.jz@bp.renesas.com>
Tue, 2 Aug 2022 10:15:33 +0000 (11:15 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 24 Oct 2022 07:57:25 +0000 (09:57 +0200)
[ Upstream commit 13dec051c7f139eef345c55a60941843e72128f1 ]

As per the RZ/V2L Hardware User's Manual (Rev.1.00 Nov, 2021),
the interrupt type of SCI{Rx,Tx} is edge triggered.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Fixes: 7c2b8198f4f321df ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC")
Link: https://lore.kernel.org/r/20220802101534.1401342-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/renesas/r9a07g054.dtsi

index 4d6b9d7684c94600993d7a75db78e72543231c39..d0eeca4f6aa1b68b36ed25f00ad601434cbeab03 100644 (file)
                        compatible = "renesas,r9a07g054-sci", "renesas,sci";
                        reg = <0 0x1004d000 0 0x400>;
                        interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "eri", "rxi", "txi", "tei";
                        clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
                        compatible = "renesas,r9a07g054-sci", "renesas,sci";
                        reg = <0 0x1004d400 0 0x400>;
                        interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
-                                    <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
                                     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-names = "eri", "rxi", "txi", "tei";
                        clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;