]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
mmc: sdhci-esdhc-imx: refactor clock loopback selection logic
authorLuke Wang <ziniu.wang_1@nxp.com>
Wed, 21 May 2025 02:55:01 +0000 (10:55 +0800)
committerUlf Hansson <ulf.hansson@linaro.org>
Tue, 24 Jun 2025 10:43:22 +0000 (12:43 +0200)
i.MX reference manual specifies that internal clock loopback should be
used for SDR104/HS200/HS400 modes. Move ESDHC_MIX_CTRL_FBCLK_SEL
configuration into the timing selection function to:

1. Explicitly set internal loopback path for SDR104/HS200/HS400 modes
2. Avoid redundant bit manipulation across multiple functions

Preserve ESDHC_MIX_CTRL_FBCLK_SEL during system resume for SDIO devices
with MMC_PM_KEEP_POWER and MMC_PM_WAKE_SDIO_IRQ flag, as the controller
might lose register state during suspend while skipping card
re-initialization.

Signed-off-by: Luke Wang <ziniu.wang_1@nxp.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20250521025502.112030-1-ziniu.wang_1@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/sdhci-esdhc-imx.c

index 05dd2b563c02a75df1074ec2efd9af26ef0b040e..1b51137803c934e9e20121f4465b62ae66761310 100644 (file)
@@ -728,23 +728,17 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
                writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
                if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
                        u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS);
-                       u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
-                       if (val & SDHCI_CTRL_TUNED_CLK) {
+                       if (val & SDHCI_CTRL_TUNED_CLK)
                                v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
-                       } else {
+                       else
                                v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
-                               m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
-                       }
 
-                       if (val & SDHCI_CTRL_EXEC_TUNING) {
+                       if (val & SDHCI_CTRL_EXEC_TUNING)
                                v |= ESDHC_MIX_CTRL_EXE_TUNE;
-                               m |= ESDHC_MIX_CTRL_FBCLK_SEL;
-                       } else {
+                       else
                                v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
-                       }
 
                        writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS);
-                       writel(m, host->ioaddr + ESDHC_MIX_CTRL);
                }
                return;
        case SDHCI_TRANSFER_MODE:
@@ -1082,7 +1076,6 @@ static void esdhc_reset_tuning(struct sdhci_host *host)
                ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
                if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
                        ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
-                       ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
                        writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL);
                        writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
                } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
@@ -1177,8 +1170,7 @@ static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
                "warning! RESET_ALL never complete before sending tuning command\n");
 
        reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
-       reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
-                       ESDHC_MIX_CTRL_FBCLK_SEL;
+       reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL;
        writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
        writel(FIELD_PREP(ESDHC_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK, val),
               host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
@@ -1432,6 +1424,15 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
                break;
        }
 
+       if (timing == MMC_TIMING_UHS_SDR104 ||
+           timing == MMC_TIMING_MMC_HS200 ||
+           timing == MMC_TIMING_MMC_HS400)
+               m |= ESDHC_MIX_CTRL_FBCLK_SEL;
+       else
+               m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
+
+       writel(m, host->ioaddr + ESDHC_MIX_CTRL);
+
        esdhc_change_pinstate(host, timing);
 }