]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: qcom: sm8550: Add ACD levels for GPU
authorAaron Kling <webgeek1234@gmail.com>
Sun, 8 Feb 2026 01:20:00 +0000 (19:20 -0600)
committerBjorn Andersson <andersson@kernel.org>
Wed, 18 Mar 2026 12:13:15 +0000 (07:13 -0500)
Update GPU node to include acd level values.

Signed-off-by: Aaron Kling <webgeek1234@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260207-sm8550-acd-v1-1-53d084c58c9a@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arch/arm64/boot/dts/qcom/sm8550.dtsi

index 7bbbf3109bc2c6e2e6445207cc86c401be482a73..412a3b2dabd03fc52ee95414107d91c9387aed43 100644 (file)
                                        opp-hz = /bits/ 64 <680000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
                                        opp-peak-kBps = <16500000>;
+                                       qcom,opp-acd-level = <0x882e5ffd>;
                                };
 
                                opp-615000000 {
                                        opp-hz = /bits/ 64 <615000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
                                        opp-peak-kBps = <12449218>;
+                                       qcom,opp-acd-level = <0xa82f5ffd>;
                                };
 
                                opp-550000000 {
                                        opp-hz = /bits/ 64 <550000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
                                        opp-peak-kBps = <10687500>;
+                                       qcom,opp-acd-level = <0xe0285ffd>;
                                };
 
                                opp-475000000 {
                                        opp-hz = /bits/ 64 <475000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
                                        opp-peak-kBps = <6074218>;
+                                       qcom,opp-acd-level = <0xe0285ffd>;
                                };
 
                                opp-401000000 {
                                        opp-hz = /bits/ 64 <401000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
                                        opp-peak-kBps = <6074218>;
+                                       qcom,opp-acd-level = <0xc02a5ffd>;
                                };
 
                                opp-348000000 {
                                        opp-hz = /bits/ 64 <348000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
                                        opp-peak-kBps = <6074218>;
+                                       qcom,opp-acd-level = <0xe02b5ffd>;
                                };
 
                                opp-295000000 {
                                        opp-hz = /bits/ 64 <295000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
                                        opp-peak-kBps = <6074218>;
+                                       qcom,opp-acd-level = <0xe02d5ffd>;
                                };
 
                                opp-220000000 {
                                        opp-hz = /bits/ 64 <220000000>;
                                        opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
                                        opp-peak-kBps = <2136718>;
+                                       qcom,opp-acd-level = <0xc02f5ffd>;
                                };
                        };
                };