In ARM mode: enable LDRD/STRD of the form "reg, [reg], reg"

git-svn-id: svn://svn.valgrind.org/vex/trunk@2034

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index 91ba65dac748ce47aac14355c3b50a0a0a3d357e..5c8a462719933f87b2e256fd008d61c7cf229909 100644 (file)
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -13858,7 +13858,6 @@ DisResult disInstr_ARM_WRK (
    }
    else if (INSN(27,24) == BITS4(0,0,0,0) && INSN(22,20) == BITS3(0,0,0)) {
       summary = 3 | 32;
-      goto decode_failure; //ATC
    }
    else goto after_load_store_doubleword;