Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 68c266467bb24a371ed92874e34ecfa9fd273a84..99b44cf52e23f0590ee7f316f03ffc7892ccaa62 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,78 @@
+2023-05-21  Georg-Johann Lay  <avr@gjlay.de>
+
+       PR target/90622
+       * config/avr/avr.cc (avr_fold_builtin) [AVR_BUILTIN_INSERT_BITS]:
+       Don't fold to XOR / AND / XOR if just one bit is copied to the
+       same position.
+
+2023-05-21  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * config/nvptx/nvptx.cc (nvptx_expand_brev): Expand target
+       builtin for bit reversal using brev instruction.
+       (enum nvptx_builtins): Add NVPTX_BUILTIN_BREV and
+       NVPTX_BUILTIN_BREVLL.
+       (nvptx_init_builtins): Define "brev" and "brevll".
+       (nvptx_expand_builtin): Expand NVPTX_BUILTIN_BREV and
+       NVPTX_BUILTIN_BREVLL via nvptx_expand_brev function.
+       * doc/extend.texi (Nvidia PTX Builtin-in Functions): New
+       section, document __builtin_nvptx_brev{,ll}.
+
+2023-05-21  Jakub Jelinek  <jakub@redhat.com>
+
+       PR tree-optimization/109505
+       * match.pd ((x | CST1) & CST2 -> (x & CST2) | (CST1 & CST2),
+       Combine successive equal operations with constants,
+       (A +- CST1) +- CST2 -> A + CST3, (CST1 - A) +- CST2 -> CST3 - A,
+       CST1 - (CST2 - A) -> CST3 + A): Use ! on ops with 2 CONSTANT_CLASS_P
+       operands.
+
+2023-05-21  Andrew Pinski  <apinski@marvell.com>
+
+       * expr.cc (expand_single_bit_test): Correct bitpos for big-endian.
+
+2023-05-21  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/genrvv-type-indexer.cc (BOOL_SIZE_LIST): Add the
+       rest bool size, aka 2, 4, 8, 16, 32, 64.
+       * config/riscv/riscv-vector-builtins-functions.def (vreinterpret):
+       Register vbool[2|4|8|16|32|64] interpret function.
+       * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_BOOL2_INTERPRET_OPS):
+       New macro for vbool2_t.
+       (DEF_RVV_BOOL4_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL8_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL16_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL32_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL64_INTERPRET_OPS): Likewise.
+       (vint8m1_t): Add the type to bool[2|4|8|16|32|64]_interpret_ops.
+       (vint16m1_t): Likewise.
+       (vint32m1_t): Likewise.
+       (vint64m1_t): Likewise.
+       (vuint8m1_t): Likewise.
+       (vuint16m1_t): Likewise.
+       (vuint32m1_t): Likewise.
+       (vuint64m1_t): Likewise.
+       * config/riscv/riscv-vector-builtins.cc (DEF_RVV_BOOL2_INTERPRET_OPS):
+       New macro for vbool2_t.
+       (DEF_RVV_BOOL4_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL8_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL16_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL32_INTERPRET_OPS): Likewise.
+       (DEF_RVV_BOOL64_INTERPRET_OPS): Likewise.
+       (required_extensions_p): Add vbool[2|4|8|16|32|64] interpret case.
+       * config/riscv/riscv-vector-builtins.def (bool2_interpret): Add
+       vbool2_t interprect to base type.
+       (bool4_interpret): Likewise.
+       (bool8_interpret): Likewise.
+       (bool16_interpret): Likewise.
+       (bool32_interpret): Likewise.
+       (bool64_interpret): Likewise.
+
+2023-05-21  Andrew Pinski  <apinski@marvell.com>
+
+       PR middle-end/109919
+       * expr.cc (expand_single_bit_test): Don't use the
+       target for expand_expr.
+
 2023-05-20  Gerald Pfeifer  <gerald@pfeifer.com>
 
        * doc/install.texi (Specific): Remove de facto empty alpha*-*-*

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 7b10b7bde803a4dfdcbc1d303849c49b55b6b206..f25bef13f1e9a2430b9109c0f2aa3dbf1d53edf8 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20230521
+20230522

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4dc720bf1c3ce1ef4198811543fab3b01720e97d..992e54c4a87ff819736c3a8f2055a201deee5c25 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,25 @@
+2023-05-21  Roger Sayle  <roger@nextmovesoftware.com>
+
+       * gcc.target/nvptx/brev-1.c: New 32-bit test case.
+       * gcc.target/nvptx/brev-2.c: Likewise.
+       * gcc.target/nvptx/brevll-1.c: New 64-bit test case.
+       * gcc.target/nvptx/brevll-2.c: Likewise.
+
+2023-05-21  Jakub Jelinek  <jakub@redhat.com>
+
+       PR tree-optimization/109505
+       * gcc.target/aarch64/sve/pr109505.c: New test.
+
+2023-05-21  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Add
+       test cases for vbool[2|4|8|16|32|64]_t.
+
+2023-05-21  Andrew Pinski  <apinski@marvell.com>
+
+       PR middle-end/109919
+       * gcc.c-torture/compile/pr109919-1.c: New test.
+
 2023-05-20  Triffid Hunter  <triffid.hunter@gmail.com>
 
        PR target/105753

diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 4e42e0ca9b901533fdce76d7f673889325a653a3..f238d987fc8f12342489fb245ea0debffe06553a 100644 (file)
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,13 @@
+2023-05-21  Tobias Burnus  <tobias@codesourcery.com>
+
+       PR libgomp/109875
+       * config/gcn/target.c (GOMP_teams4): Honor nteams-var ICV.
+       * config/nvptx/target.c (GOMP_teams4): Likewise.
+       * testsuite/libgomp.c-c++-common/teams-nteams-icv-1.c: New test.
+       * testsuite/libgomp.c-c++-common/teams-nteams-icv-2.c: New test.
+       * testsuite/libgomp.c-c++-common/teams-nteams-icv-3.c: New test.
+       * testsuite/libgomp.c-c++-common/teams-nteams-icv-4.c: New test.
+
 2023-05-19  Jakub Jelinek  <jakub@redhat.com>
 
        PR libgomp/109904