drm/amd/display: Ensure link output is disabled in backend reset for PLL_ON

[Why]
We're missing the code to actually disable the link output when we have
to leave the SYMCLK_ON but the TX remains OFF.

[How]
Port the code from DCN401 that detects SYMCLK_ON_TX_OFF and disable
the link output when the backend is reset.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index d1ecdb92b072b1cbd8a92e205963b36489ebe1d0..20f700b59847cf8b3f6e62ca784117d20adbd2c6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -546,8 +546,22 @@ static void dcn31_reset_back_end_for_pipe(
        if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
                pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
                                pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
+       /*
+        * TODO - convert symclk_ref_cnts for otg to a bit map to solve
+        * the case where the same symclk is shared across multiple otg
+        * instances
+        */
        if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
-               pipe_ctx->stream->link->phy_state.symclk_ref_cnts.otg = 0;
+               link->phy_state.symclk_ref_cnts.otg = 0;
+
+       if (pipe_ctx->top_pipe == NULL) {
+               if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) {
+                       const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
+
+                       link_hwss->disable_link_output(link, &pipe_ctx->link_res, pipe_ctx->stream->signal);
+                       link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
+               }
+       }
 
        set_drr_and_clear_adjust_pending(pipe_ctx, pipe_ctx->stream, NULL);