Daily bump.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f21a656b8e1db82bac0f22b52f22802fc3d2ba5d..0795d650e34e7526943cdcd2eb1b23a8d771e655 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,51 @@
+2023-11-05  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.h (enum reg_class): Add LEGACY_INDEX_REGS.
+       Rename LEGACY_REGS to LEGACY_GENERAL_REGS.
+       (REG_CLASS_NAMES): Ditto.
+       (REG_CLASS_CONTENTS): Ditto.
+       * config/i386/constraints.md ("R"): Update for rename.
+
+2023-11-05  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * mode-switching.cc: Remove unused forward references.
+       (seginfo): Remove bbnum.
+       (new_seginfo): Remove associated argument.
+       (optimize_mode_switching): Update calls accordingly.
+
+2023-11-05  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * read-rtl.cc (read_rtx_operand): Avoid spinning endlessly for
+       invalid [...] operands.
+
+2023-11-05  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/112105
+       * config/aarch64/aarch64.cc (aarch64_modes_compatible_p): New
+       function, with the core logic extracted from...
+       (aarch64_can_change_mode_class): ...here.  Extend the previous rules
+       to allow changes between partial SVE modes and other modes if
+       the other mode is no bigger than an element, and if no other rule
+       prevents it.  Use the aarch64_modes_tieable_p handling of
+       partial Advanced SIMD structure modes.
+       (aarch64_modes_tieable_p): Use aarch64_modes_compatible_p.
+       Allow all vector mode ties that it allows.
+
+2023-11-05  Pan Li  <pan2.li@intel.com>
+
+       * config/riscv/autovec.md: Remove the size check of lrint.
+       * config/riscv/riscv-v.cc (emit_vec_narrow_cvt_x_f): New help
+       emit func impl.
+       (emit_vec_widden_cvt_x_f): New help emit func impl.
+       (emit_vec_rounding_to_integer): New func impl to emit the
+       rounding from FP to integer.
+       (expand_vec_lrint): Leverage emit_vec_rounding_to_integer.
+       * config/riscv/vector.md: Take V_VLSF for vfncvt.
+
+2023-11-05  Juzhe-Zhong  <juzhe.zhong@rivai.ai>
+
+       * config/riscv/vector.md: Fix bug.
+
 2023-11-04  Sergei Trofimovich  <siarheit@google.com>
 
        PR bootstrap/112379

diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP
index 39983b1bc266c328233e55a02a7bee0c27763b62..189b7225e9297ab3b8aeec9ccea5db26fe36d6e4 100644 (file)
--- a/gcc/DATESTAMP
+++ b/gcc/DATESTAMP
@@ -1 +1 @@
-20231105
+20231106

diff --git a/gcc/c-family/ChangeLog b/gcc/c-family/ChangeLog
index 1cf06aad11ebeae6626587cc91216c26f79c6199..a2079ffcf98abb11223cbfca28ea6ef3b8907fd1 100644 (file)
--- a/gcc/c-family/ChangeLog
+++ b/gcc/c-family/ChangeLog
@@ -1,3 +1,10 @@
+2023-11-05  Jakub Jelinek  <jakub@redhat.com>
+
+       * c-lex.cc (c_common_has_attribute): Return 1 for omp::directive
+       and omp::sequence with -fopenmp or -fopenmp-simd also for C, not
+       just for C++.  Return 1 for omp::decl with -fopenmp or -fopenmp-simd
+       for both C and C++.
+
 2023-11-04  David Malcolm  <dmalcolm@redhat.com>
 
        * c-pragma.cc:: (handle_pragma_push_options): Fix missing "GCC" in

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e60aa6ce850d554759028cd7bb80cabce526c1d6..3375974a972f6bdd9622d98b489a9876902f9bec 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,37 @@
+2023-11-05  Francois-Xavier Coudert  <fxcoudert@gcc.gnu.org>
+
+       * gcc.target/i386/pr111753.c: Require dfp.
+
+2023-11-05  Jakub Jelinek  <jakub@redhat.com>
+
+       * c-c++-common/gomp/attrs-1.c: Adjust for omp::directive and
+       omp::sequence being supported also in C and add tests for omp::decl.
+       * c-c++-common/gomp/attrs-2.c: Likewise.
+       * c-c++-common/gomp/attrs-3.c: Add tests for omp::decl.
+
+2023-11-05  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/112105
+       * gcc.target/aarch64/pr112105.c: New test.
+       * gcc.target/aarch64/sve/pcs/struct_3_128.c: Expect a 32-bit spill
+       rather than a 16-bit spill.
+
+2023-11-05  Pan Li  <pan2.li@intel.com>
+
+       * gcc.target/riscv/rvv/autovec/unop/math-irint-run-0.c:
+       * gcc.target/riscv/rvv/autovec/unop/math-irint-1.c: New test.
+       * gcc.target/riscv/rvv/autovec/unop/math-irintf-run-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/unop/math-llrintf-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/unop/math-llrintf-run-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/unop/math-lrint-rv32-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/unop/math-lrint-rv32-run-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/unop/math-lrintf-rv64-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/unop/math-lrintf-rv64-run-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/vls/math-irint-1.c: New test.
+       * gcc.target/riscv/rvv/autovec/vls/math-llrintf-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/vls/math-lrint-rv32-0.c: New test.
+       * gcc.target/riscv/rvv/autovec/vls/math-lrintf-rv64-0.c: New test.
+
 2023-11-04  Jakub Jelinek  <jakub@redhat.com>
 
        * gcc.dg/gomp/attrs-19.c: New test.

diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog
index 1073dfa7f805cf0a938d8b07a9a63ad877577f2c..e2a674667a007aa74e7fa5230aa7118ff866154d 100644 (file)
--- a/libgomp/ChangeLog
+++ b/libgomp/ChangeLog
@@ -1,3 +1,8 @@
+2023-11-05  Jakub Jelinek  <jakub@redhat.com>
+
+       * libgomp.texi (Enabling OpenMP): Adjust wording for attribute syntax
+       supported also in C.
+
 2023-10-31  Thomas Schwinge  <thomas@codesourcery.com>
 
        * testsuite/libgomp.oacc-c-c++-common/deep-copy-8.c: Add OpenACC