phy: rockchip: samsung-hdptx: Optimize internal rate handling

Drop the rate parameter from a bunch of internal helpers and, instead,
make better use of the newly introduced ->hdmi_cfg.tmds_char_rate driver
data.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250318-phy-sam-hdptx-bpc-v6-13-8cb1678e7663@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index a19a89233d808e2b38f6e7e58a1dc38ddd7cadd3..d09e1f7b25ec131d3c40fb52564cad27dce3b2d4 100644 (file)
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -968,31 +968,34 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate,
        return true;
 }
 
-static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
-                                         unsigned long long rate)
+static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx)
 {
        const struct ropll_config *cfg = NULL;
        struct ropll_config rc = {0};
        int ret, i;
 
+       if (!hdptx->hdmi_cfg.tmds_char_rate)
+               return 0;
+
        for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
-               if (rate == ropll_tmds_cfg[i].rate) {
+               if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) {
                        cfg = &ropll_tmds_cfg[i];
                        break;
                }
 
        if (!cfg) {
-               if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) {
-                       cfg = &rc;
-               } else {
-                       dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
+               if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) {
+                       dev_err(hdptx->dev, "%s cannot find pll cfg for rate=%llu\n",
+                               __func__, hdptx->hdmi_cfg.tmds_char_rate);
                        return -EINVAL;
                }
+
+               cfg = &rc;
        }
 
        dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n",
-               __func__, rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
-               cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
+               __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv + 1,
+               cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
 
        rk_hdptx_pre_power_up(hdptx);
 
@@ -1030,19 +1033,18 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
 
        ret = rk_hdptx_post_enable_pll(hdptx);
        if (!ret)
-               hdptx->hw_rate = rate;
+               hdptx->hw_rate = hdptx->hdmi_cfg.tmds_char_rate;
 
        return ret;
 }
 
-static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
-                                          unsigned long long rate)
+static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx)
 {
        rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
 
        regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
 
-       if (rate > HDMI14_MAX_RATE) {
+       if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) {
                /* For 1/40 bitrate clk */
                rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
        } else {
@@ -1094,8 +1096,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx)
                     HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0));
 }
 
-static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
-                                    unsigned long long rate)
+static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
 {
        enum phy_mode mode = phy_get_mode(hdptx->phy);
        u32 status;
@@ -1114,11 +1115,9 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
        if (mode == PHY_MODE_DP) {
                rk_hdptx_dp_reset(hdptx);
        } else {
-               if (rate) {
-                       ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
-                       if (ret)
-                               goto dec_usage;
-               }
+               ret = rk_hdptx_ropll_tmds_cmn_config(hdptx);
+               if (ret)
+                       goto dec_usage;
        }
 
        return 0;
@@ -1431,7 +1430,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
                dev_dbg(hdptx->dev, "%s rate=%llu\n", __func__, hdptx->hdmi_cfg.tmds_char_rate);
        }
 
-       ret = rk_hdptx_phy_consumer_get(hdptx, hdptx->hdmi_cfg.tmds_char_rate);
+       ret = rk_hdptx_phy_consumer_get(hdptx);
        if (ret)
                return ret;
 
@@ -1462,7 +1461,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
                regmap_write(hdptx->grf, GRF_HDPTX_CON0,
                             HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
 
-               ret = rk_hdptx_ropll_tmds_mode_config(hdptx, hdptx->hdmi_cfg.tmds_char_rate);
+               ret = rk_hdptx_ropll_tmds_mode_config(hdptx);
                if (ret)
                        rk_hdptx_phy_consumer_put(hdptx, true);
        }
@@ -1830,7 +1829,7 @@ static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
 {
        struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
 
-       return rk_hdptx_phy_consumer_get(hdptx, hdptx->hw_rate);
+       return rk_hdptx_phy_consumer_get(hdptx);
 }
 
 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
@@ -1897,7 +1896,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
         * while the latter being executed only once, i.e. when clock remains
         * in the prepared state during rate changes.
         */
-       return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
+       return rk_hdptx_ropll_tmds_cmn_config(hdptx);
 }
 
 static const struct clk_ops hdptx_phy_clk_ops = {