net: stmmac: stm32: use stmmac_get_phy_intf_sel()

Use stmmac_get_phy_intf_sel() to decode the PHY interface mode to the
phy_intf_sel value. As both configure functions would end up with the
same code, call this from stm32mp1_set_mode(), validate the result and
pass the resulting value into the stm32 configure function. Use this
value to set the operating mode for the DWMAC core.

Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/E1vIjUU-0000000Dqtz-2PwT@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
index 18d26f096f5f763616cc95da2cccd9ac98921cea..e1b260ed4790b96f81cb4b202eeaf1a919b3702b 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
@@ -227,16 +227,17 @@ static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat)
        return -EINVAL;
 }
 
-static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
+static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat,
+                                  u8 phy_intf_sel)
 {
        struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
        u32 reg = dwmac->mode_reg;
-       u8 phy_intf_sel;
-       int val = 0;
+       int val;
+
+       val = FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, phy_intf_sel);
 
        switch (plat_dat->phy_interface) {
        case PHY_INTERFACE_MODE_MII:
-               phy_intf_sel = PHY_INTF_SEL_GMII_MII;
                /*
                 * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
                 * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
@@ -247,12 +248,10 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
                        val |= SYSCFG_PMCR_ETH_SEL_MII;
                break;
        case PHY_INTERFACE_MODE_GMII:
-               phy_intf_sel = PHY_INTF_SEL_GMII_MII;
                if (dwmac->enable_eth_ck)
                        val |= SYSCFG_PMCR_ETH_CLK_SEL;
                break;
        case PHY_INTERFACE_MODE_RMII:
-               phy_intf_sel = PHY_INTF_SEL_RMII;
                if (dwmac->enable_eth_ck)
                        val |= SYSCFG_PMCR_ETH_REF_CLK_SEL;
                break;
@@ -260,7 +259,6 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
        case PHY_INTERFACE_MODE_RGMII_ID:
        case PHY_INTERFACE_MODE_RGMII_RXID:
        case PHY_INTERFACE_MODE_RGMII_TXID:
-               phy_intf_sel = PHY_INTF_SEL_RGMII;
                if (dwmac->enable_eth_ck)
                        val |= SYSCFG_PMCR_ETH_CLK_SEL;
                break;
@@ -273,8 +271,6 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
 
        dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface));
 
-       val |= FIELD_PREP(SYSCFG_PMCR_PHY_INTF_SEL_MASK, phy_intf_sel);
-
        /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */
        val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);
 
@@ -287,19 +283,20 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
                                 dwmac->mode_mask, val);
 }
 
-static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
+static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat,
+                                    u8 phy_intf_sel)
 {
        struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
-       u8 phy_intf_sel = PHY_INTF_SEL_GMII_MII;
        u32 reg = dwmac->mode_reg;
-       int val = 0;
+       int val;
+
+       val = FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, phy_intf_sel);
 
        switch (plat_dat->phy_interface) {
        case PHY_INTERFACE_MODE_MII:
                /* ETH_REF_CLK_SEL bit in SYSCFG register is not applicable in MII mode */
                break;
        case PHY_INTERFACE_MODE_RMII:
-               phy_intf_sel = PHY_INTF_SEL_RMII;
                if (dwmac->enable_eth_ck) {
                        /* Internal clock ETH_CLK of 50MHz from RCC is used */
                        val |= SYSCFG_ETHCR_ETH_REF_CLK_SEL;
@@ -309,8 +306,6 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
        case PHY_INTERFACE_MODE_RGMII_ID:
        case PHY_INTERFACE_MODE_RGMII_RXID:
        case PHY_INTERFACE_MODE_RGMII_TXID:
-               phy_intf_sel = PHY_INTF_SEL_RGMII;
-               fallthrough;
        case PHY_INTERFACE_MODE_GMII:
                if (dwmac->enable_eth_ck) {
                        /* Internal clock ETH_CLK of 125MHz from RCC is used */
@@ -326,8 +321,6 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
 
        dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->phy_interface));
 
-       val |= FIELD_PREP(SYSCFG_ETHCR_ETH_SEL_MASK, phy_intf_sel);
-
        /* Select PTP (IEEE1588) clock selection from RCC (ck_ker_ethxptp) */
        val |= SYSCFG_ETHCR_ETH_PTP_CLK_SEL;
 
@@ -339,7 +332,7 @@ static int stm32mp2_configure_syscfg(struct plat_stmmacenet_data *plat_dat)
 static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
 {
        struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
-       int ret;
+       int phy_intf_sel, ret;
 
        ret = stm32mp1_select_ethck_external(plat_dat);
        if (ret)
@@ -349,10 +342,19 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
        if (ret)
                return ret;
 
+       phy_intf_sel = stmmac_get_phy_intf_sel(plat_dat->phy_interface);
+       if (phy_intf_sel != PHY_INTF_SEL_GMII_MII &&
+           phy_intf_sel != PHY_INTF_SEL_RGMII &&
+           phy_intf_sel != PHY_INTF_SEL_RMII) {
+               dev_err(dwmac->dev, "Mode %s not supported\n",
+                       phy_modes(plat_dat->phy_interface));
+               return phy_intf_sel < 0 ? phy_intf_sel : -EINVAL;
+       }
+
        if (!dwmac->ops->is_mp2)
-               return stm32mp1_configure_pmcr(plat_dat);
+               return stm32mp1_configure_pmcr(plat_dat, phy_intf_sel);
        else
-               return stm32mp2_configure_syscfg(plat_dat);
+               return stm32mp2_configure_syscfg(plat_dat, phy_intf_sel);
 }
 
 static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat)