drm/i915: pass dev_priv explicitly to TRANS_VBLANK

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the TRANS_VBLANK register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c33739ac6f26105fd1ad79b0027b6626e241c7bc.1717514638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f95709321ea61fec509f12e33d23a79720fbc9cb..0ee42954054f54d0a7d9f2c231f0ea1512bbcdc5 100644 (file)
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -995,7 +995,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
        if (DISPLAY_VER(dev_priv) >= 12) {
                for_each_dsi_port(port, intel_dsi->ports) {
                        dsi_trans = dsi_port_to_transcoder(port);
-                       intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
+                       intel_de_write(dev_priv,
+                                      TRANS_VBLANK(dev_priv, dsi_trans),
                                       VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
                }
        }

diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 29ab5b112b86e4d56129a65099d27f1d0b49a708..54549d2cfcff52e9d5f0fa546a7297980524a8c6 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -710,7 +710,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
        save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
        save_vtotal = intel_de_read(dev_priv,
                                    TRANS_VTOTAL(dev_priv, cpu_transcoder));
-       vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
+       vblank = intel_de_read(dev_priv,
+                              TRANS_VBLANK(dev_priv, cpu_transcoder));
 
        vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
        vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
@@ -749,7 +750,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
                        u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
 
                        vblank_start = vsync_start;
-                       intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+                       intel_de_write(dev_priv,
+                                      TRANS_VBLANK(dev_priv, cpu_transcoder),
                                       VBLANK_START(vblank_start - 1) |
                                       VBLANK_END(vblank_end - 1));
                        restore_vblank = true;
@@ -782,7 +784,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 
                /* restore vblank if necessary */
                if (restore_vblank)
-                       intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);
+                       intel_de_write(dev_priv,
+                                      TRANS_VBLANK(dev_priv, cpu_transcoder),
+                                      vblank);
                /*
                 * If more than 3/4 of the scanline detected a monitor,
                 * then it is assumed to be present. This works even on i830,

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c681a23be1eb151aae900c8602c0769910a7e10b..87a690cf5808b084ecab13af058758bb3aee476b 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2723,7 +2723,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
        intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
                       VACTIVE(crtc_vdisplay - 1) |
                       VTOTAL(crtc_vtotal - 1));
-       intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+       intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
                       VBLANK_START(crtc_vblank_start - 1) |
                       VBLANK_END(crtc_vblank_end - 1));
        intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
@@ -2760,7 +2760,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
         * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
         * But let's write it anyway to keep the state checker happy.
         */
-       intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+       intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
                       VBLANK_START(crtc_vblank_start - 1) |
                       VBLANK_END(crtc_vblank_end - 1));
        /*
@@ -2832,7 +2832,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
 
        /* FIXME TGL+ DSI transcoders have this! */
        if (!transcoder_is_dsi(cpu_transcoder)) {
-               tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
+               tmp = intel_de_read(dev_priv,
+                                   TRANS_VBLANK(dev_priv, cpu_transcoder));
                adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
                adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
        }
@@ -8198,7 +8199,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
                       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
        intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder),
                       VACTIVE(480 - 1) | VTOTAL(525 - 1));
-       intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+       intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder),
                       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
        intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
                       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 611a9cd2596f4529550f93bafe2abac9bed3745a..03a33ff2653a2e4a8ac412c38d5995ea7fa1ef01 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -233,7 +233,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
        intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
                       intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)));
        intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
-                      intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
+                      intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder)));
        intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
                       intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));
        intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fe61cd0dae6ec353e3affc47e7a94fbbd6fb6a80..31b059acd56fc9fd0ae2a6c7e34d21c8ba40da44 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1140,7 +1140,7 @@
 #define TRANS_HBLANK(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A)
 #define TRANS_HSYNC(dev_priv, trans)   _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A)
 #define TRANS_VTOTAL(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A)
-#define TRANS_VBLANK(trans)    _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
+#define TRANS_VBLANK(dev_priv, trans)  _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A)
 #define TRANS_VSYNC(trans)     _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A)
 #define BCLRPAT(trans)         _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A)
 #define TRANS_VSYNCSHIFT(trans)        _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A)

diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 5dd85943e0a13841fac6d7ce3423b23f89795b7b..baeedcdfdcab23b8f31705a42aa82e0d84b43f43 100644 (file)
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -235,7 +235,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A));
-       MMIO_D(TRANS_VBLANK(TRANSCODER_A));
+       MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A));
        MMIO_D(TRANS_VSYNC(TRANSCODER_A));
        MMIO_D(BCLRPAT(TRANSCODER_A));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
@@ -244,7 +244,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B));
-       MMIO_D(TRANS_VBLANK(TRANSCODER_B));
+       MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B));
        MMIO_D(TRANS_VSYNC(TRANSCODER_B));
        MMIO_D(BCLRPAT(TRANSCODER_B));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
@@ -253,7 +253,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C));
-       MMIO_D(TRANS_VBLANK(TRANSCODER_C));
+       MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C));
        MMIO_D(TRANS_VSYNC(TRANSCODER_C));
        MMIO_D(BCLRPAT(TRANSCODER_C));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
@@ -262,7 +262,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
        MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP));
-       MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
+       MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP));
        MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
        MMIO_D(BCLRPAT(TRANSCODER_EDP));
        MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));