drm/xe: Drop unnecessary STOP_RING clearing

The STOP_RING bit in MI_MODE is already clear by default out of hardware
reset and will only be '1' if the driver intentionally sets it after
that.

The logic of clearing this bit appears to originate from very
early (pre-GuC, pre-execlist) code in i915 where we needed to stop the
ring before performing a host-initiated engine reset; after the reset
the STOP_RING bit needed to be cleared to allow execution to resume.

None of that is relevant to Xe (or even modern i915) since STOP_RING
isn't necessary for execlist-based engine resets (and even if it were,
Xe doesn't initiate any engine resets; the GuC handles that now).

Bspec: 60356, 60184
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260424-engine-setup-v2-8-59cc620a25f1@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
index 4d5cd1b6f50d9c191930f6c1af86bd61c64d2a3f..c4c879a9e555dd51479f396dcde1410485b56e9f 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
@@ -176,7 +176,6 @@
 #define RING_TIMESTAMP_UDW(base)               XE_REG((base) + 0x358 + 4)
 #define   RING_VALID_MASK                      0x00000001
 #define   RING_VALID                           0x00000001
-#define   STOP_RING                            REG_BIT(8)
 
 #define RING_CTX_TIMESTAMP(base)               XE_REG((base) + 0x3a8)
 #define RING_CTX_TIMESTAMP_UDW(base)           XE_REG((base) + 0x3ac)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index b380d3cf6d3a93bd42a6f9af867e6a6da7bdbcd3..91e644067cc42b7dfb2ed22f94f0eae9d3815c61 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -327,9 +327,6 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
 {
        xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
                                  xe_bo_ggtt_addr(hwe->hwsp));
-       xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0),
-                                 REG_MASKED_FIELD_DISABLE(STOP_RING));
-       xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0));
 }
 
 static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe,

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index c725cde4508d2082955436ca0cbf84f37a202252..9db914584347311f07104523af6559f048a6d029 100644 (file)
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -682,25 +682,6 @@ static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe)
        }
 }
 
-static int lrc_ring_mi_mode(struct xe_hw_engine *hwe)
-{
-       struct xe_device *xe = gt_to_xe(hwe->gt);
-
-       if (GRAPHICS_VERx100(xe) >= 1250)
-               return 0x70;
-       else
-               return 0x60;
-}
-
-static void reset_stop_ring(u32 *regs, struct xe_hw_engine *hwe)
-{
-       int x;
-
-       x = lrc_ring_mi_mode(hwe);
-       regs[x + 1] &= ~STOP_RING;
-       regs[x + 1] |= STOP_RING << 16;
-}
-
 static inline bool xe_lrc_has_indirect_ring_state(struct xe_lrc *lrc)
 {
        return lrc->flags & XE_LRC_FLAG_INDIRECT_RING_STATE;
@@ -980,7 +961,6 @@ static void *empty_lrc_data(struct xe_hw_engine *hwe)
        set_offsets(regs, reg_offsets(gt_to_xe(gt), hwe->class), hwe);
        set_context_control(regs, hwe);
        set_memory_based_intr(regs, hwe);
-       reset_stop_ring(regs, hwe);
        if (xe_gt_has_indirect_ring_state(gt)) {
                regs = data + xe_gt_lrc_size(gt, hwe->class) -
                       LRC_INDIRECT_RING_STATE_SIZE;