# if defined(VGP_ppc32_aix5)
- vg_assert(0 == sizeof(VexGuestPPC32State) % 8);
+ vg_assert(0 == sizeof(VexGuestPPC32State) % 16);
/* Zero out the initial state, and set up the simulated FPU in a
sane way. */
# else /* defined(VGP_ppc64_aix5) */
- vg_assert(0 == sizeof(VexGuestPPC64State) % 8);
+ vg_assert(0 == sizeof(VexGuestPPC64State) % 16);
/* Zero out the initial state, and set up the simulated FPU in a
sane way. */
all other registers zeroed. */
# if defined(VGP_x86_linux)
- vg_assert(0 == sizeof(VexGuestX86State) % 8);
+ vg_assert(0 == sizeof(VexGuestX86State) % 16);
/* Zero out the initial state, and set up the simulated FPU in a
sane way. */
asm volatile("movw %%ss, %0" : : "m" (arch->vex.guest_SS));
# elif defined(VGP_amd64_linux)
- vg_assert(0 == sizeof(VexGuestAMD64State) % 8);
+ vg_assert(0 == sizeof(VexGuestAMD64State) % 16);
/* Zero out the initial state, and set up the simulated FPU in a
sane way. */
arch->vex.guest_RIP = iifii.initial_client_IP;
# elif defined(VGP_ppc32_linux)
- vg_assert(0 == sizeof(VexGuestPPC32State) % 8);
+ vg_assert(0 == sizeof(VexGuestPPC32State) % 16);
/* Zero out the initial state, and set up the simulated FPU in a
sane way. */