gcc/ChangeLog:

2019-10-15  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>

	* config/arm/vfp.md (fma<SDF:mode>4): Enable DF only when
	TARGET_VFP_DOUBLE.
	(*fmsub<SDF:mode>4): Likewise.
	*fnmsub<SDF:mode>4): Likewise.
	(*fnmadd<SDF:mode>4): Likewise.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@276977 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b58f60cc2ab965606234887165242f4a8dc38813..9957d2cbc744871dfb5f50531764aad32f2f6cf4 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2019-10-15  Kugan Vivekanandarajah  <kugan.vivekanandarajah@linaro.org>
+
+       * config/arm/vfp.md (fma<SDF:mode>4): Enable DF only when
+       TARGET_VFP_DOUBLE.
+       (*fmsub<SDF:mode>4): Likewise.
+       *fnmsub<SDF:mode>4): Likewise.
+       (*fnmadd<SDF:mode>4): Likewise.
+
 2019-10-14 Joel Hutton  <Joel.Hutton@arm.com>
 
        * doc/tree-ssa.texi: Update renamed macro name.

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 661919e2357d352d12ff1020dc061f0c8d052841..1979aa6fdb423450a22ecf31f019b8c7ba15c903 100644 (file)
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -1321,7 +1321,7 @@
         (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
                 (match_operand:SDF 2 "register_operand" "<F_constraint>")
                 (match_operand:SDF 3 "register_operand" "0")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]
@@ -1357,7 +1357,7 @@
                                             "<F_constraint>"))
                 (match_operand:SDF 2 "register_operand" "<F_constraint>")
                 (match_operand:SDF 3 "register_operand" "0")))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]
@@ -1379,7 +1379,7 @@
        (fma:SDF (match_operand:SDF 1 "register_operand" "<F_constraint>")
                 (match_operand:SDF 2 "register_operand" "<F_constraint>")
                 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfnms%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]
@@ -1402,7 +1402,7 @@
                                               "<F_constraint>"))
                 (match_operand:SDF 2 "register_operand" "<F_constraint>")
                 (neg:SDF (match_operand:SDF 3 "register_operand" "0"))))]
-  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA"
+  "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FMA <vfp_double_cond>"
   "vfnma%?.<V_if_elem>\\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
   [(set_attr "predicable" "yes")
    (set_attr "type" "ffma<vfp_type>")]