arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs

[ Upstream commit a7ab6f946683e065fa22db1cc2f2748d4584178a ]

The original addition of cache information for the Amlogic S922X SoC
used the wrong next-level cache node for CPU cores 100 and 101,
incorrectly referencing `l2_cache_l`. These cores actually belong to
the big cluster and should reference `l2_cache_b`. Update the device
tree accordingly.

Fixes: e7f85e6c155a ("arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC")
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20251123-fixkhadas-v1-1-045348f0a4c2@baylibre.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index f04efa8282561cec866c38a27a2ce15c67498c66..23358d94844c94539c82bfabf0d5c990afab99d8 100644 (file)
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -87,7 +87,7 @@
                        i-cache-line-size = <32>;
                        i-cache-size = <0x8000>;
                        i-cache-sets = <32>;
-                       next-level-cache = <&l2_cache_l>;
+                       next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
                };
 
@@ -103,7 +103,7 @@
                        i-cache-line-size = <32>;
                        i-cache-size = <0x8000>;
                        i-cache-sets = <32>;
-                       next-level-cache = <&l2_cache_l>;
+                       next-level-cache = <&l2_cache_b>;
                        #cooling-cells = <2>;
                };