extern void amd64g_dirtyhelper_CPUID_sse3_and_cx16 ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_CPUID_sse42_and_cx16 ( VexGuestAMD64State* st );
extern void amd64g_dirtyhelper_CPUID_avx_and_cx16 ( VexGuestAMD64State* st );
-extern void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st );
+extern void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st,
+ ULong hasF16C, ULong hasRDRAND );
extern void amd64g_dirtyhelper_FINIT ( VexGuestAMD64State* );
extern void amd64g_dirtyhelper_SxDT ( void* address,
ULong op /* 0 or 1 */ );
+// This returns a 32-bit value from the host's RDRAND in bits 31:0, and the
+// resulting C flag value in bit 32.
+extern ULong amd64g_dirtyhelper_RDRAND ( void );
+
+
/* Helps with PCMP{I,E}STR{I,M}.
CALLED FROM GENERATED CODE: DIRTY HELPER(s). (But not really,
address sizes : 39 bits physical, 48 bits virtual
power management:
*/
-void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st )
+void amd64g_dirtyhelper_CPUID_avx2 ( VexGuestAMD64State* st,
+ ULong hasF16C, ULong hasRDRAND )
{
+ vassert((hasF16C >> 1) == 0ULL);
+ vassert((hasRDRAND >> 1) == 0ULL);
# define SET_ABCD(_a,_b,_c,_d) \
do { st->guest_RAX = (ULong)(_a); \
st->guest_RBX = (ULong)(_b); \
case 0x00000000:
SET_ABCD(0x0000000d, 0x756e6547, 0x6c65746e, 0x49656e69);
break;
- case 0x00000001:
- /* Don't advertise RDRAND support, bit 30 in ECX. */
- SET_ABCD(0x000306c3, 0x02100800, 0x3ffafbff, 0xbfebfbff);
+ case 0x00000001: {
+ // As a baseline, advertise neither F16C (ecx:29) nor RDRAND (ecx:30),
+ // but patch in support for them as directed by the caller.
+ UInt ecx_extra
+ = (hasF16C ? (1U << 29) : 0) | (hasRDRAND ? (1U << 30) : 0);
+ SET_ABCD(0x000306c3, 0x02100800, (0x1ffafbff | ecx_extra), 0xbfebfbff);
break;
+ }
case 0x00000002:
SET_ABCD(0x76036301, 0x00f0b6ff, 0x00000000, 0x00c10000);
break;
# endif
}
+/* CALLED FROM GENERATED CODE */
+/* DIRTY HELPER (non-referentially-transparent) */
+/* Horrible hack. On non-amd64 platforms, do nothing. On amd64 targets, get a
+ 32 bit random number using RDRAND, and return it and the associated rflags.C
+ value. */
+ULong amd64g_dirtyhelper_RDRAND ( void ) {
+# if defined(__x86_64__)
+ ULong res = 0;
+ ULong cflag = 0;
+ __asm__ __volatile__(
+ "movq $0, %%r11 ; "
+ "movq $0, %%r12 ; "
+ "rdrand %%r11d ; "
+ "setc %%r12b ; "
+ "movq %%r11, %0 ; "
+ "movq %%r12, %1"
+ : "=r"(res), "=r"(cflag) : : "r11", "r12"
+ );
+ res &= 0xFFFFFFFFULL;
+ cflag &= 1ULL;
+ return (cflag << 32) | res;
+# else
+ /* There's nothing we can sensibly do. Return a value denoting
+ "I succeeded, and the random bits are all zero" :-/ */
+ return 1ULL << 32;
+# endif
+}
+
/*---------------------------------------------------------------*/
/*--- Helpers for MMX/SSE/SSE2. ---*/
/*---------------------------------------------------------------*/
toBool((pfx & (PFX_F2|PFX_F3)) == PFX_F2);
}
+/* Return True iff pfx has F2 and F3 clear */
+static Bool haveNoF2noF3 ( Prefix pfx )
+{
+ return
+ toBool((pfx & (PFX_F2|PFX_F3)) == 0);
+}
+
/* Return True iff pfx has 66, F2 and F3 clear */
static Bool haveNo66noF2noF3 ( Prefix pfx )
{
}
+/* Handles 128 and 256 bit versions of VCVTPH2PS. */
+static Long dis_VCVTPH2PS ( const VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool is256bit )
+{
+ /* This is a width-doubling load or reg-reg move, that does conversion on the
+ transferred data. */
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp srcE = newTemp(is256bit ? Ity_V128 : Ity_I64);
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ assign(srcE, is256bit ? unop(Iop_V256toV128_0, getYMMReg(rE))
+ : unop(Iop_V128to64, getXMMReg(rE)));
+ delta += 1;
+ DIP("vcvtph2ps %s,%s\n", nameXMMReg(rE),
+ (is256bit ? nameYMMReg: nameXMMReg)(rG));
+ } else {
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp addr = disAMode(&alen, vbi, pfx, delta, dis_buf, 0);
+ // I don't think we need an alignment check here (not 100% sure tho.)
+ assign(srcE, loadLE(is256bit ? Ity_V128 : Ity_I64, mkexpr(addr)));
+ delta += alen;
+ DIP( "vcvtph2ps %s,%s\n", dis_buf,
+ (is256bit ? nameYMMReg: nameXMMReg)(rG));
+ }
+
+ IRExpr* res = unop(is256bit ? Iop_F16toF32x8 : Iop_F16toF32x4, mkexpr(srcE));
+ (is256bit ? putYMMReg : putYMMRegLoAndZU)(rG, res);
+
+ return delta;
+}
+
+
/* Handles 128 bit versions of PMOVZXBW and PMOVSXBW. */
static Long dis_PMOVxXBW_128 ( const VexAbiInfo* vbi, Prefix pfx,
Long delta, Bool isAvx, Bool xIsZ )
}
vassert(fName); vassert(fAddr);
- d = unsafeIRDirty_0_N ( 0/*regparms*/,
- fName, fAddr, mkIRExprVec_1(IRExpr_GSPTR()) );
+ IRExpr** args = NULL;
+ if (fAddr == &amd64g_dirtyhelper_CPUID_avx2) {
+ Bool hasF16C = (archinfo->hwcaps & VEX_HWCAPS_AMD64_F16C) != 0;
+ Bool hasRDRAND = (archinfo->hwcaps & VEX_HWCAPS_AMD64_RDRAND) != 0;
+ args = mkIRExprVec_3(IRExpr_GSPTR(),
+ mkIRExpr_HWord(hasF16C ? 1 : 0),
+ mkIRExpr_HWord(hasRDRAND ? 1 : 0));
+ } else {
+ args = mkIRExprVec_1(IRExpr_GSPTR());
+ }
+ d = unsafeIRDirty_0_N ( 0/*regparms*/, fName, fAddr, args );
+
/* declare guest state effects */
d->nFxState = 4;
vex_bzero(&d->fxState, sizeof(d->fxState));
return delta;
}
- case 0xC7: { /* CMPXCHG8B Ev, CMPXCHG16B Ev */
- IRType elemTy = sz==4 ? Ity_I32 : Ity_I64;
- IRTemp expdHi = newTemp(elemTy);
- IRTemp expdLo = newTemp(elemTy);
- IRTemp dataHi = newTemp(elemTy);
- IRTemp dataLo = newTemp(elemTy);
- IRTemp oldHi = newTemp(elemTy);
- IRTemp oldLo = newTemp(elemTy);
- IRTemp flags_old = newTemp(Ity_I64);
- IRTemp flags_new = newTemp(Ity_I64);
- IRTemp success = newTemp(Ity_I1);
- IROp opOR = sz==4 ? Iop_Or32 : Iop_Or64;
- IROp opXOR = sz==4 ? Iop_Xor32 : Iop_Xor64;
- IROp opCasCmpEQ = sz==4 ? Iop_CasCmpEQ32 : Iop_CasCmpEQ64;
- IRExpr* zero = sz==4 ? mkU32(0) : mkU64(0);
- IRTemp expdHi64 = newTemp(Ity_I64);
- IRTemp expdLo64 = newTemp(Ity_I64);
-
- /* Translate this using a DCAS, even if there is no LOCK
- prefix. Life is too short to bother with generating two
- different translations for the with/without-LOCK-prefix
- cases. */
- *expect_CAS = True;
-
- /* Decode, and generate address. */
- if (have66(pfx)) goto decode_failure;
- if (sz != 4 && sz != 8) goto decode_failure;
- if (sz == 8 && !(archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16))
- goto decode_failure;
+ case 0xC7: {
modrm = getUChar(delta);
- if (epartIsReg(modrm)) goto decode_failure;
- if (gregLO3ofRM(modrm) != 1) goto decode_failure;
- if (haveF2orF3(pfx)) {
- /* Since the e-part is memory only, F2 or F3 (one or the
- other) is acceptable if LOCK is also present. But only
- for cmpxchg8b. */
- if (sz == 8) goto decode_failure;
- if (haveF2andF3(pfx) || !haveLOCK(pfx)) goto decode_failure;
- }
- addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
- delta += alen;
+ // Detecting valid CMPXCHG combinations is pretty complex.
+ Bool isValidCMPXCHG = gregLO3ofRM(modrm) == 1;
+ if (isValidCMPXCHG) {
+ if (have66(pfx)) isValidCMPXCHG = False;
+ if (sz != 4 && sz != 8) isValidCMPXCHG = False;
+ if (sz == 8 && !(archinfo->hwcaps & VEX_HWCAPS_AMD64_CX16))
+ isValidCMPXCHG = False;
+ if (epartIsReg(modrm)) isValidCMPXCHG = False;
+ if (haveF2orF3(pfx)) {
+ /* Since the e-part is memory only, F2 or F3 (one or the
+ other) is acceptable if LOCK is also present. But only
+ for cmpxchg8b. */
+ if (sz == 8) isValidCMPXCHG = False;
+ if (haveF2andF3(pfx) || !haveLOCK(pfx)) isValidCMPXCHG = False;
+ }
+ }
+
+ /* 0F C7 /1 (with qualifications) = CMPXCHG */
+ if (isValidCMPXCHG) {
+ // Note that we've already read the modrm byte by this point, but we
+ // haven't moved delta past it.
+ IRType elemTy = sz==4 ? Ity_I32 : Ity_I64;
+ IRTemp expdHi = newTemp(elemTy);
+ IRTemp expdLo = newTemp(elemTy);
+ IRTemp dataHi = newTemp(elemTy);
+ IRTemp dataLo = newTemp(elemTy);
+ IRTemp oldHi = newTemp(elemTy);
+ IRTemp oldLo = newTemp(elemTy);
+ IRTemp flags_old = newTemp(Ity_I64);
+ IRTemp flags_new = newTemp(Ity_I64);
+ IRTemp success = newTemp(Ity_I1);
+ IROp opOR = sz==4 ? Iop_Or32 : Iop_Or64;
+ IROp opXOR = sz==4 ? Iop_Xor32 : Iop_Xor64;
+ IROp opCasCmpEQ = sz==4 ? Iop_CasCmpEQ32 : Iop_CasCmpEQ64;
+ IRExpr* zero = sz==4 ? mkU32(0) : mkU64(0);
+ IRTemp expdHi64 = newTemp(Ity_I64);
+ IRTemp expdLo64 = newTemp(Ity_I64);
+
+ /* Translate this using a DCAS, even if there is no LOCK
+ prefix. Life is too short to bother with generating two
+ different translations for the with/without-LOCK-prefix
+ cases. */
+ *expect_CAS = True;
- /* cmpxchg16b requires an alignment check. */
- if (sz == 8)
- gen_SEGV_if_not_16_aligned( addr );
+ /* Generate address */
+ vassert(!epartIsReg(modrm));
+ addr = disAMode ( &alen, vbi, pfx, delta, dis_buf, 0 );
+ delta += alen;
- /* Get the expected and new values. */
- assign( expdHi64, getIReg64(R_RDX) );
- assign( expdLo64, getIReg64(R_RAX) );
-
- /* These are the correctly-sized expected and new values.
- However, we also get expdHi64/expdLo64 above as 64-bits
- regardless, because we will need them later in the 32-bit
- case (paradoxically). */
- assign( expdHi, sz==4 ? unop(Iop_64to32, mkexpr(expdHi64))
- : mkexpr(expdHi64) );
- assign( expdLo, sz==4 ? unop(Iop_64to32, mkexpr(expdLo64))
- : mkexpr(expdLo64) );
- assign( dataHi, sz==4 ? getIReg32(R_RCX) : getIReg64(R_RCX) );
- assign( dataLo, sz==4 ? getIReg32(R_RBX) : getIReg64(R_RBX) );
-
- /* Do the DCAS */
- stmt( IRStmt_CAS(
- mkIRCAS( oldHi, oldLo,
- Iend_LE, mkexpr(addr),
- mkexpr(expdHi), mkexpr(expdLo),
- mkexpr(dataHi), mkexpr(dataLo)
- )));
-
- /* success when oldHi:oldLo == expdHi:expdLo */
- assign( success,
- binop(opCasCmpEQ,
- binop(opOR,
- binop(opXOR, mkexpr(oldHi), mkexpr(expdHi)),
- binop(opXOR, mkexpr(oldLo), mkexpr(expdLo))
- ),
- zero
- ));
-
- /* If the DCAS is successful, that is to say oldHi:oldLo ==
- expdHi:expdLo, then put expdHi:expdLo back in RDX:RAX,
- which is where they came from originally. Both the actual
- contents of these two regs, and any shadow values, are
- unchanged. If the DCAS fails then we're putting into
- RDX:RAX the value seen in memory. */
- /* Now of course there's a complication in the 32-bit case
- (bah!): if the DCAS succeeds, we need to leave RDX:RAX
- unchanged; but if we use the same scheme as in the 64-bit
- case, we get hit by the standard rule that a write to the
- bottom 32 bits of an integer register zeros the upper 32
- bits. And so the upper halves of RDX and RAX mysteriously
- become zero. So we have to stuff back in the original
- 64-bit values which we previously stashed in
- expdHi64:expdLo64, even if we're doing a cmpxchg8b. */
- /* It's just _so_ much fun ... */
- putIRegRDX( 8,
- IRExpr_ITE( mkexpr(success),
- mkexpr(expdHi64),
- sz == 4 ? unop(Iop_32Uto64, mkexpr(oldHi))
- : mkexpr(oldHi)
- ));
- putIRegRAX( 8,
- IRExpr_ITE( mkexpr(success),
- mkexpr(expdLo64),
- sz == 4 ? unop(Iop_32Uto64, mkexpr(oldLo))
- : mkexpr(oldLo)
- ));
-
- /* Copy the success bit into the Z flag and leave the others
- unchanged */
- assign( flags_old, widenUto64(mk_amd64g_calculate_rflags_all()));
- assign(
- flags_new,
- binop(Iop_Or64,
- binop(Iop_And64, mkexpr(flags_old),
- mkU64(~AMD64G_CC_MASK_Z)),
- binop(Iop_Shl64,
- binop(Iop_And64,
- unop(Iop_1Uto64, mkexpr(success)), mkU64(1)),
- mkU8(AMD64G_CC_SHIFT_Z)) ));
+ /* cmpxchg16b requires an alignment check. */
+ if (sz == 8)
+ gen_SEGV_if_not_16_aligned( addr );
- stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
- stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(flags_new) ));
- stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
- /* Set NDEP even though it isn't used. This makes
- redundant-PUT elimination of previous stores to this field
- work better. */
- stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+ /* Get the expected and new values. */
+ assign( expdHi64, getIReg64(R_RDX) );
+ assign( expdLo64, getIReg64(R_RAX) );
+
+ /* These are the correctly-sized expected and new values.
+ However, we also get expdHi64/expdLo64 above as 64-bits
+ regardless, because we will need them later in the 32-bit
+ case (paradoxically). */
+ assign( expdHi, sz==4 ? unop(Iop_64to32, mkexpr(expdHi64))
+ : mkexpr(expdHi64) );
+ assign( expdLo, sz==4 ? unop(Iop_64to32, mkexpr(expdLo64))
+ : mkexpr(expdLo64) );
+ assign( dataHi, sz==4 ? getIReg32(R_RCX) : getIReg64(R_RCX) );
+ assign( dataLo, sz==4 ? getIReg32(R_RBX) : getIReg64(R_RBX) );
+
+ /* Do the DCAS */
+ stmt( IRStmt_CAS(
+ mkIRCAS( oldHi, oldLo,
+ Iend_LE, mkexpr(addr),
+ mkexpr(expdHi), mkexpr(expdLo),
+ mkexpr(dataHi), mkexpr(dataLo)
+ )));
- /* Sheesh. Aren't you glad it was me and not you that had to
- write and validate all this grunge? */
+ /* success when oldHi:oldLo == expdHi:expdLo */
+ assign( success,
+ binop(opCasCmpEQ,
+ binop(opOR,
+ binop(opXOR, mkexpr(oldHi), mkexpr(expdHi)),
+ binop(opXOR, mkexpr(oldLo), mkexpr(expdLo))
+ ),
+ zero
+ ));
+
+ /* If the DCAS is successful, that is to say oldHi:oldLo ==
+ expdHi:expdLo, then put expdHi:expdLo back in RDX:RAX,
+ which is where they came from originally. Both the actual
+ contents of these two regs, and any shadow values, are
+ unchanged. If the DCAS fails then we're putting into
+ RDX:RAX the value seen in memory. */
+ /* Now of course there's a complication in the 32-bit case
+ (bah!): if the DCAS succeeds, we need to leave RDX:RAX
+ unchanged; but if we use the same scheme as in the 64-bit
+ case, we get hit by the standard rule that a write to the
+ bottom 32 bits of an integer register zeros the upper 32
+ bits. And so the upper halves of RDX and RAX mysteriously
+ become zero. So we have to stuff back in the original
+ 64-bit values which we previously stashed in
+ expdHi64:expdLo64, even if we're doing a cmpxchg8b. */
+ /* It's just _so_ much fun ... */
+ putIRegRDX( 8,
+ IRExpr_ITE( mkexpr(success),
+ mkexpr(expdHi64),
+ sz == 4 ? unop(Iop_32Uto64, mkexpr(oldHi))
+ : mkexpr(oldHi)
+ ));
+ putIRegRAX( 8,
+ IRExpr_ITE( mkexpr(success),
+ mkexpr(expdLo64),
+ sz == 4 ? unop(Iop_32Uto64, mkexpr(oldLo))
+ : mkexpr(oldLo)
+ ));
+
+ /* Copy the success bit into the Z flag and leave the others
+ unchanged */
+ assign( flags_old, widenUto64(mk_amd64g_calculate_rflags_all()));
+ assign(
+ flags_new,
+ binop(Iop_Or64,
+ binop(Iop_And64, mkexpr(flags_old),
+ mkU64(~AMD64G_CC_MASK_Z)),
+ binop(Iop_Shl64,
+ binop(Iop_And64,
+ unop(Iop_1Uto64, mkexpr(success)), mkU64(1)),
+ mkU8(AMD64G_CC_SHIFT_Z)) ));
- DIP("cmpxchg8b %s\n", dis_buf);
- return delta;
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(flags_new) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ /* Set NDEP even though it isn't used. This makes
+ redundant-PUT elimination of previous stores to this field
+ work better. */
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+
+ /* Sheesh. Aren't you glad it was me and not you that had to
+ write and validate all this grunge? */
+
+ DIP("cmpxchg8b %s\n", dis_buf);
+ return delta;
+ } // if (isValidCMPXCHG)
+
+ /* 0F C7 /6 no-F2-or-F3 = RDRAND */
+ if (gregLO3ofRM(modrm) == 6/*RDRAND*/
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_RDRAND)
+ && epartIsReg(modrm) && haveNoF2noF3(pfx)
+ && (sz == 8 || sz == 4 || sz == 2)) {
+ delta++; // move past modrm
+ IRType ty = szToITy(sz);
+
+ // Pull a first 32 bits of randomness, plus C flag, out of the host.
+ IRTemp pairLO = newTemp(Ity_I64);
+ IRDirty* dLO
+ = unsafeIRDirty_1_N(pairLO, 0/*regparms*/,
+ "amd64g_dirtyhelper_RDRAND",
+ &amd64g_dirtyhelper_RDRAND, mkIRExprVec_0());
+ // There are no guest state or memory effects to declare for |dLO|.
+ stmt( IRStmt_Dirty(dLO) );
+
+ IRTemp randsLO = newTemp(Ity_I32);
+ assign(randsLO, unop(Iop_64to32, mkexpr(pairLO)));
+ IRTemp cLO = newTemp(Ity_I64);
+ assign(cLO, binop(Iop_Shr64, mkexpr(pairLO), mkU8(32)));
+
+ // We'll assemble the final pairing in (cFinal, randsNearlyFinal).
+ IRTemp randsNearlyFinal = newTemp(Ity_I64);
+ IRTemp cFinal = newTemp(Ity_I64);
+
+ if (ty == Ity_I64) {
+ // Pull another 32 bits of randomness out of the host.
+ IRTemp pairHI = newTemp(Ity_I64);
+ IRDirty* dHI
+ = unsafeIRDirty_1_N(pairHI, 0/*regparms*/,
+ "amd64g_dirtyhelper_RDRAND",
+ &amd64g_dirtyhelper_RDRAND, mkIRExprVec_0());
+ // There are no guest state or memory effects to declare for |dHI|.
+ stmt( IRStmt_Dirty(dHI) );
+
+ IRTemp randsHI = newTemp(Ity_I32);
+ assign(randsHI, unop(Iop_64to32, mkexpr(pairHI)));
+ IRTemp cHI = newTemp(Ity_I64);
+ assign(cHI, binop(Iop_Shr64, mkexpr(pairHI), mkU8(32)));
+ assign(randsNearlyFinal, binop(Iop_32HLto64,
+ mkexpr(randsHI), mkexpr(randsLO)));
+ assign(cFinal, binop(Iop_And64,
+ binop(Iop_And64, mkexpr(cHI), mkexpr(cLO)),
+ mkU64(1)));
+ } else {
+ assign(randsNearlyFinal, unop(Iop_32Uto64, mkexpr(randsLO)));
+ assign(cFinal, binop(Iop_And64, mkexpr(cLO), mkU64(1)));
+ }
+
+ /* Now cFinal[0] is the final success/failure flag (cFinal[0] == 1
+ means success). But there's another twist. If we failed then the
+ returned value must be forced to zero. Otherwise we could have the
+ situation, when sz==8, where one of the host calls failed but the
+ other didn't. This would give cFinal[0] == 0 (correctly) but
+ randsNearlyFinal not being zero, because it contains the 32 bit
+ result of the non-failing call. */
+ IRTemp randsFinal = newTemp(Ity_I64);
+ assign(randsFinal,
+ binop(Iop_And64,
+ mkexpr(randsNearlyFinal),
+ binop(Iop_Sar64,
+ binop(Iop_Shl64, mkexpr(cFinal), mkU8(63)),
+ mkU8(63))
+ ));
+
+ // So, finally, update the guest state.
+ putIRegE(sz, pfx, modrm, narrowTo(ty, mkexpr(randsFinal)));
+
+ // Set C=<success indication>, O,S,Z,A,P = 0. cFinal has already been
+ // masked so only the lowest bit remains.
+ stmt( IRStmt_Put( OFFB_CC_OP, mkU64(AMD64G_CC_OP_COPY) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP1, mkexpr(cFinal) ));
+ stmt( IRStmt_Put( OFFB_CC_DEP2, mkU64(0) ));
+ stmt( IRStmt_Put( OFFB_CC_NDEP, mkU64(0) ));
+
+ DIP("rdrand %s", nameIRegE(sz, pfx, modrm));
+ return delta;
+ }
+
+ goto decode_failure;
}
case 0xC8: /* BSWAP %eax */
}
break;
+ case 0x13:
+ /* VCVTPH2PS xmm2/m64, xmm1 = VEX.128.66.0F38.W0 13 /r */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_F16C)) {
+ delta = dis_VCVTPH2PS( vbi, pfx, delta, /*is256bit=*/False );
+ goto decode_success;
+ }
+ /* VCVTPH2PS xmm2/m128, xmm1 = VEX.256.66.0F38.W0 13 /r */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_F16C)) {
+ delta = dis_VCVTPH2PS( vbi, pfx, delta, /*is256bit=*/True );
+ goto decode_success;
+ }
+ break;
+
case 0x16:
/* VPERMPS ymm3/m256, ymm2, ymm1 = VEX.NDS.256.66.0F38.W0 16 /r */
if (have66noF2noF3(pfx)
return res;
}
+/* Handles 128 and 256 bit versions of VCVTPS2PH. */
+static Long dis_VCVTPS2PH ( const VexAbiInfo* vbi, Prefix pfx,
+ Long delta, Bool is256bit )
+{
+ /* This is a width-halving store or reg-reg move, that does conversion on the
+ transferred data. */
+ UChar modrm = getUChar(delta);
+ UInt rG = gregOfRexRM(pfx, modrm);
+ IRTemp rm = newTemp(Ity_I32);
+ IROp op = is256bit ? Iop_F32toF16x8 : Iop_F32toF16x4;
+ IRExpr* srcG = (is256bit ? getYMMReg : getXMMReg)(rG);
+
+ /* (imm & 3) contains an Intel-encoded rounding mode. Because that encoding
+ is the same as the encoding for IRRoundingMode, we can use that value
+ directly in the IR as a rounding mode. */
+
+ if (epartIsReg(modrm)) {
+ UInt rE = eregOfRexRM(pfx, modrm);
+ delta += 1;
+ UInt imm = getUChar(delta);
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+ IRExpr* res = binop(op, mkexpr(rm), srcG);
+ if (!is256bit)
+ res = unop(Iop_64UtoV128, res);
+ putYMMRegLoAndZU(rE, res);
+ DIP("vcvtps2ph $%u,%s,%s\n",
+ imm, (is256bit ? nameYMMReg : nameXMMReg)(rG), nameXMMReg(rE));
+ } else {
+ Int alen = 0;
+ HChar dis_buf[50];
+ IRTemp addr = disAMode( &alen, vbi, pfx, delta, dis_buf, 1 );
+ delta += alen;
+ UInt imm = getUChar(delta);
+ assign(rm, (imm & 4) ? get_sse_roundingmode() : mkU32(imm & 3));
+ IRExpr* res = binop(op, mkexpr(rm), srcG);
+ storeLE(mkexpr(addr), res);
+ DIP("vcvtps2ph $%u,%s,%s\n",
+ imm, (is256bit ? nameYMMReg : nameXMMReg)(rG), dis_buf);
+ }
+ delta++;
+ /* doesn't use vvvv */
+ return delta;
+}
+
__attribute__((noinline))
static
Long dis_ESC_0F3A__VEX (
}
break;
+ case 0x1D:
+ /* VCVTPS2PH imm8, xmm2, xmm1/m64 = VEX.128.66.0F3A.W0 1D /r ib */
+ if (have66noF2noF3(pfx)
+ && 0==getVexL(pfx)/*128*/ && 0==getRexW(pfx)/*W0*/
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_F16C)) {
+ delta = dis_VCVTPS2PH( vbi, pfx, delta, /*is256bit=*/False );
+ goto decode_success;
+ }
+ /* VCVTPS2PH imm8, ymm2, ymm1/m128 = VEX.256.66.0F3A.W0 1D /r ib */
+ if (have66noF2noF3(pfx)
+ && 1==getVexL(pfx)/*256*/ && 0==getRexW(pfx)/*W0*/
+ && (archinfo->hwcaps & VEX_HWCAPS_AMD64_F16C)) {
+ delta = dis_VCVTPS2PH( vbi, pfx, delta, /*is256bit=*/True );
+ goto decode_success;
+ }
+ break;
+
case 0x20:
/* VPINSRB r32/m8, xmm2, xmm1 = VEX.NDS.128.66.0F3A.W0 20 /r ib */
if (have66noF2noF3(pfx)
case Asse_UNPCKLQ: return "punpcklq";
case Asse_PSHUFB: return "pshufb";
case Asse_PMADDUBSW: return "pmaddubsw";
+ case Asse_F32toF16: return "vcvtps2ph(rm_field=$0x4).";
+ case Asse_F16toF32: return "vcvtph2ps.";
default: vpanic("showAMD64SseOp");
}
}
|| i->Ain.Sse32Fx4.op == Asse_RSQRTF
|| i->Ain.Sse32Fx4.op == Asse_SQRTF
|| i->Ain.Sse32Fx4.op == Asse_I2F
- || i->Ain.Sse32Fx4.op == Asse_F2I );
+ || i->Ain.Sse32Fx4.op == Asse_F2I
+ || i->Ain.Sse32Fx4.op == Asse_F32toF16
+ || i->Ain.Sse32Fx4.op == Asse_F16toF32 );
addHRegUse(u, HRmRead, i->Ain.Sse32Fx4.src);
addHRegUse(u, unary ? HRmWrite : HRmModify,
i->Ain.Sse32Fx4.dst);
i->Ain.SseLdzLO.addr);
goto done;
- case Ain_Sse32Fx4:
+ case Ain_Sse32Fx4: {
+ UInt srcRegNo = vregEnc3210(i->Ain.Sse32Fx4.src);
+ UInt dstRegNo = vregEnc3210(i->Ain.Sse32Fx4.dst);
+ // VEX encoded cases
+ switch (i->Ain.Sse32Fx4.op) {
+ case Asse_F16toF32: { // vcvtph2ps %xmmS, %xmmD
+ UInt s = srcRegNo;
+ UInt d = dstRegNo;
+ // VCVTPH2PS %xmmS, %xmmD (s and d are both xmm regs, range 0 .. 15)
+ // 0xC4 : ~d3 1 ~s3 0 0 0 1 0 : 0x79 : 0x13 : 1 1 d2 d1 d0 s2 s1 s0
+ UInt byte2 = ((((~d)>>3)&1)<<7) | (1<<6)
+ | ((((~s)>>3)&1)<<5) | (1<<1);
+ UInt byte5 = (1<<7) | (1<<6) | ((d&7) << 3) | ((s&7) << 0);
+ *p++ = 0xC4;
+ *p++ = byte2;
+ *p++ = 0x79;
+ *p++ = 0x13;
+ *p++ = byte5;
+ goto done;
+ }
+ case Asse_F32toF16: { // vcvtps2ph $4, %xmmS, %xmmD
+ UInt s = srcRegNo;
+ UInt d = dstRegNo;
+ // VCVTPS2PH $4, %xmmS, %xmmD (s and d both xmm regs, range 0 .. 15)
+ // 0xC4 : ~s3 1 ~d3 0 0 0 1 1 : 0x79
+ // : 0x1D : 11 s2 s1 s0 d2 d1 d0 : 0x4
+ UInt byte2 = ((((~s)>>3)&1)<<7) | (1<<6)
+ | ((((~d)>>3)&1)<<5) | (1<<1) | (1 << 0);
+ UInt byte5 = (1<<7) | (1<<6) | ((s&7) << 3) | ((d&7) << 0);
+ *p++ = 0xC4;
+ *p++ = byte2;
+ *p++ = 0x79;
+ *p++ = 0x1D;
+ *p++ = byte5;
+ *p++ = 0x04;
+ goto done;
+ }
+ default: break;
+ }
+ // After this point, REX encoded cases only
xtra = 0;
switch (i->Ain.Sse32Fx4.op) {
case Asse_F2I: *p++ = 0x66; break;
default: break;
}
- *p++ = clearWBit(
- rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse32Fx4.dst),
- vregEnc3210(i->Ain.Sse32Fx4.src) ));
+ *p++ = clearWBit(rexAMode_R_enc_enc(dstRegNo, srcRegNo));
*p++ = 0x0F;
switch (i->Ain.Sse32Fx4.op) {
case Asse_ADDF: *p++ = 0x58; break;
case Asse_CMPUNF: *p++ = 0xC2; xtra = 0x103; break;
default: goto bad;
}
- p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse32Fx4.dst),
- vregEnc3210(i->Ain.Sse32Fx4.src) );
+ p = doAMode_R_enc_enc(p, dstRegNo, srcRegNo);
if (xtra & 0x100)
*p++ = toUChar(xtra & 0xFF);
goto done;
+ }
case Ain_Sse64Fx2:
xtra = 0;
Asse_UNPCKLB, Asse_UNPCKLW, Asse_UNPCKLD, Asse_UNPCKLQ,
// Only for SSSE3 capable hosts:
Asse_PSHUFB,
- Asse_PMADDUBSW
+ Asse_PMADDUBSW,
+ // Only for F16C capable hosts:
+ Asse_F32toF16, // F32 to F16 conversion, aka vcvtps2ph
+ Asse_F16toF32, // F16 to F32 conversion, aka vcvtph2ps
}
AMD64SseOp;
return dst;
}
+ // Half-float vector conversion
+ if (e->Iex.Binop.op == Iop_F32toF16x4
+ && (env->hwcaps & VEX_HWCAPS_AMD64_F16C)) {
+ HReg srcV = iselVecExpr(env, e->Iex.Binop.arg2);
+ HReg dstV = newVRegV(env);
+ HReg dstI = newVRegI(env);
+ set_SSE_rounding_mode( env, e->Iex.Binop.arg1 );
+ addInstr(env, AMD64Instr_Sse32Fx4(Asse_F32toF16, srcV, dstV));
+ set_SSE_rounding_default(env);
+ addInstr(env, AMD64Instr_SseMOVQ(dstI, dstV, /*toXMM=*/False));
+ return dstI;
+ }
+
break;
}
}
case Iop_32UtoV128: {
+ // FIXME maybe just use MOVQ here?
HReg dst = newVRegV(env);
AMD64AMode* rsp_m32 = AMD64AMode_IR(-32, hregAMD64_RSP());
AMD64RI* ri = iselIntExpr_RI(env, e->Iex.Unop.arg);
}
case Iop_64UtoV128: {
+ // FIXME maybe just use MOVQ here?
HReg dst = newVRegV(env);
AMD64AMode* rsp0 = AMD64AMode_IR(0, hregAMD64_RSP());
AMD64RMI* rmi = iselIntExpr_RMI(env, e->Iex.Unop.arg);
return (e->Iex.Unop.op == Iop_V256toV128_1) ? vHi : vLo;
}
+ case Iop_F16toF32x4: {
+ if (env->hwcaps & VEX_HWCAPS_AMD64_F16C) {
+ HReg src = iselIntExpr_R(env, e->Iex.Unop.arg);
+ HReg dst = newVRegV(env);
+ addInstr(env, AMD64Instr_SseMOVQ(src, dst, /*toXMM=*/True));
+ addInstr(env, AMD64Instr_Sse32Fx4(Asse_F16toF32, dst, dst));
+ return dst;
+ }
+ break;
+ }
+
default:
break;
} /* switch (e->Iex.Unop.op) */
return dst;
}
+ // Half-float vector conversion
+ case Iop_F32toF16x8: {
+ if (env->hwcaps & VEX_HWCAPS_AMD64_F16C) {
+ HReg srcHi, srcLo;
+ iselDVecExpr(&srcHi, &srcLo, env, e->Iex.Binop.arg2);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ set_SSE_rounding_mode( env, e->Iex.Binop.arg1 );
+ addInstr(env, AMD64Instr_Sse32Fx4(Asse_F32toF16, srcHi, dstHi));
+ addInstr(env, AMD64Instr_Sse32Fx4(Asse_F32toF16, srcLo, dstLo));
+ set_SSE_rounding_default(env);
+ // Now we have the result in dstHi[63:0] and dstLo[63:0], but we
+ // need to compact all that into one register. There's probably a
+ // more elegant way to do this, but ..
+ addInstr(env, AMD64Instr_SseShiftN(Asse_SHL128, 64, dstHi));
+ // dstHi is now 127:64 = useful data, 63:0 = zero
+ addInstr(env, AMD64Instr_SseShiftN(Asse_SHL128, 64, dstLo));
+ addInstr(env, AMD64Instr_SseShiftN(Asse_SHR128, 64, dstLo));
+ // dstLo is now 127:64 = zero, 63:0 = useful data
+ addInstr(env, AMD64Instr_SseReRg(Asse_OR, dstHi, dstLo));
+ return dstLo;
+ }
+ break;
+ }
+
default:
break;
} /* switch (e->Iex.Binop.op) */
return;
}
+ case Iop_F16toF32x8: {
+ if (env->hwcaps & VEX_HWCAPS_AMD64_F16C) {
+ HReg src = iselVecExpr(env, e->Iex.Unop.arg);
+ HReg srcCopy = newVRegV(env);
+ HReg dstHi = newVRegV(env);
+ HReg dstLo = newVRegV(env);
+ // Copy src, since we'll need to modify it.
+ addInstr(env, mk_vMOVsd_RR(src, srcCopy));
+ addInstr(env, AMD64Instr_Sse32Fx4(Asse_F16toF32, srcCopy, dstLo));
+ addInstr(env, AMD64Instr_SseShiftN(Asse_SHR128, 64, srcCopy));
+ addInstr(env, AMD64Instr_Sse32Fx4(Asse_F16toF32, srcCopy, dstHi));
+ *rHi = dstHi;
+ *rLo = dstLo;
+ return;
+ }
+ break;
+ }
+
default:
break;
} /* switch (e->Iex.Unop.op) */
| VEX_HWCAPS_AMD64_AVX
| VEX_HWCAPS_AMD64_RDTSCP
| VEX_HWCAPS_AMD64_BMI
- | VEX_HWCAPS_AMD64_AVX2)));
+ | VEX_HWCAPS_AMD64_AVX2
+ | VEX_HWCAPS_AMD64_F16C
+ | VEX_HWCAPS_AMD64_RDRAND)));
/* Check that the host's endianness is as expected. */
vassert(archinfo_host->endness == VexEndnessLE);
case Iop_F32toI32Sx4: vex_printf("F32toI32Sx4"); return;
case Iop_F32toF16x4_DEP: vex_printf("F32toF16x4_DEP"); return;
+ case Iop_F32toF16x4: vex_printf("F32toF16x4"); return;
case Iop_F16toF32x4: vex_printf("F16toF32x4"); return;
case Iop_F16toF64x2: vex_printf("F16toF64x2"); return;
case Iop_F64toF16x2_DEP: vex_printf("F64toF16x2_DEP"); return;
case Iop_Div32Fx8: vex_printf("Div32Fx8"); return;
case Iop_I32StoF32x8: vex_printf("I32StoF32x8"); return;
case Iop_F32toI32Sx8: vex_printf("F32toI32Sx8"); return;
+ case Iop_F32toF16x8: vex_printf("F32toF16x8"); return;
+ case Iop_F16toF32x8: vex_printf("F16toF32x8"); return;
case Iop_AndV256: vex_printf("AndV256"); return;
case Iop_OrV256: vex_printf("OrV256"); return;
case Iop_XorV256: vex_printf("XorV256"); return;
case Iop_F32toI32Sx4:
BINARY(ity_RMode,Ity_V128, Ity_V128);
+ case Iop_F32toF16x4:
+ BINARY(ity_RMode,Ity_V128, Ity_I64);
+
case Iop_64HLtoV128:
BINARY(Ity_I64,Ity_I64, Ity_V128);
case Iop_F32toI32Sx8:
BINARY(ity_RMode,Ity_V256, Ity_V256);
+ case Iop_F32toF16x8:
+ BINARY(ity_RMode,Ity_V256, Ity_V128);
+
case Iop_V256toV128_1: case Iop_V256toV128_0:
UNARY(Ity_V256, Ity_V128);
+ case Iop_F16toF32x8:
+ UNARY(Ity_V128, Ity_V256);
+
case Iop_QandUQsh8x16: case Iop_QandUQsh16x8:
case Iop_QandUQsh32x4: case Iop_QandUQsh64x2:
case Iop_QandSQsh8x16: case Iop_QandSQsh16x8:
{ VEX_HWCAPS_AMD64_AVX, "avx" },
{ VEX_HWCAPS_AMD64_AVX2, "avx2" },
{ VEX_HWCAPS_AMD64_BMI, "bmi" },
+ { VEX_HWCAPS_AMD64_F16C, "f16c" },
+ { VEX_HWCAPS_AMD64_RDRAND, "rdrand" },
};
/* Allocate a large enough buffer */
static HChar buf[sizeof prefix +
#define VEX_HWCAPS_AMD64_RDTSCP (1<<9) /* RDTSCP instruction */
#define VEX_HWCAPS_AMD64_BMI (1<<10) /* BMI1 instructions */
#define VEX_HWCAPS_AMD64_AVX2 (1<<11) /* AVX2 instructions */
+#define VEX_HWCAPS_AMD64_RDRAND (1<<13) /* RDRAND instructions */
+#define VEX_HWCAPS_AMD64_F16C (1<<14) /* F16C instructions */
/* ppc32: baseline capability is integer only */
#define VEX_HWCAPS_PPC32_F (1<<8) /* basic (non-optional) FP */
/* --- Single to/from half conversion --- */
/* FIXME: what kind of rounding in F32x4 -> F16x4 case? */
// FIXME these carry no rounding mode
- Iop_F32toF16x4_DEP, /* F32x4 -> F16x4, NO ROUNDING MODE */
- Iop_F16toF32x4, /* F16x4 -> F32x4 */
+ Iop_F32toF16x4_DEP, /* F32x4(==V128) -> F16x4(==I64), NO ROUNDING MODE */
+ Iop_F32toF16x4, /* IRRoundingMode(I32) x V128 -> I64 */
+ Iop_F16toF32x4, /* F16x4 -> F32x4 */
/* -- Double to/from half conversion -- */
Iop_F64toF16x2_DEP, // F64x2 -> F16x2, NO ROUNDING MODE
Iop_I32StoF32x8, /* IRRoundingMode(I32) x V256 -> V256 */
Iop_F32toI32Sx8, /* IRRoundingMode(I32) x V256 -> V256 */
+ Iop_F32toF16x8, /* IRRoundingMode(I32) x V256 -> V128 */
+ Iop_F16toF32x8, /* F16x8(==V128) -> F32x8(==V256) */
+
Iop_Sqrt32Fx8,
Iop_Sqrt64Fx4,
Iop_RSqrtEst32Fx8,
AM_CONDITIONAL(BUILD_ADX_TESTS, test x$ac_have_as_adx = xyes)
-# Does the C compiler support the "ifunc" attribute
+# does the amd64 assembler understand the RDRAND instruction?
# Note, this doesn't generate a C-level symbol. It generates a
-# automake-level symbol (BUILD_IFUNC_TESTS), used in test Makefile.am's
+# automake-level symbol (BUILD_RDRAND_TESTS), used in test Makefile.am's
+AC_MSG_CHECKING([if amd64 assembler knows the RDRAND instruction])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+ do {
+ asm ("rdrand %r14");
+ asm ("rdrand %r14d");
+ asm ("rdrand %r14w");
+ } while (0)
+]])], [
+ac_have_as_rdrand=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_rdrand=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(BUILD_RDRAND_TESTS, test x$ac_have_as_rdrand = xyes)
+
+
+# does the amd64 assembler understand the F16C instructions (VCVTPH2PS and
+# VCVTPS2PH) ?
+# Note, this doesn't generate a C-level symbol. It generates a
+# automake-level symbol (BUILD_F16C_TESTS), used in test Makefile.am's
+AC_MSG_CHECKING([if amd64 assembler knows the F16C instructions])
+
+AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[]], [[
+ do {
+ asm ("vcvtph2ps %xmm5, %ymm10");
+ // If we put the dollar sign and zero together, the shell processing
+ // this configure.ac script substitutes the command name in. Sigh.
+ asm ("vcvtps2ph $" "0, %ymm10, %xmm5");
+ } while (0)
+]])], [
+ac_have_as_f16c=yes
+AC_MSG_RESULT([yes])
+], [
+ac_have_as_f16c=no
+AC_MSG_RESULT([no])
+])
+
+AM_CONDITIONAL(BUILD_F16C_TESTS, test x$ac_have_as_f16c = xyes)
+
+
# does the x86/amd64 assembler understand MOVBE?
# Note, this doesn't generate a C-level symbol. It generates a
# automake-level symbol (BUILD_MOVBE_TESTS), used in test Makefile.am's
#elif defined(VGA_amd64)
{ Bool have_sse3, have_ssse3, have_cx8, have_cx16;
Bool have_lzcnt, have_avx, have_bmi, have_avx2;
- Bool have_rdtscp;
+ Bool have_rdtscp, have_rdrand, have_f16c;
UInt eax, ebx, ecx, edx, max_basic, max_extended;
ULong xgetbv_0 = 0;
HChar vstr[13];
have_sse3 = have_ssse3 = have_cx8 = have_cx16
= have_lzcnt = have_avx = have_bmi = have_avx2
- = have_rdtscp = False;
+ = have_rdtscp = have_rdrand = have_f16c = False;
eax = ebx = ecx = edx = max_basic = max_extended = 0;
// we assume that SSE1 and SSE2 are available by default
have_sse3 = (ecx & (1<<0)) != 0; /* True => have sse3 insns */
have_ssse3 = (ecx & (1<<9)) != 0; /* True => have Sup SSE3 insns */
+ // fma is ecx:12
// sse41 is ecx:19
// sse42 is ecx:20
-
// xsave is ecx:26
// osxsave is ecx:27
// avx is ecx:28
- // fma is ecx:12
+ have_f16c = (ecx & (1<<29)) != 0; /* True => have F16C insns */
+ have_rdrand = (ecx & (1<<30)) != 0; /* True => have RDRAND insns */
+
have_avx = False;
/* have_fma = False; */
if ( (ecx & ((1<<28)|(1<<27)|(1<<26))) == ((1<<28)|(1<<27)|(1<<26)) ) {
have_avx2 = (ebx & (1<<5)) != 0; /* True => have AVX2 */
}
+ /* Sanity check for RDRAND and F16C. These don't actually *need* AVX2, but
+ it's convenient to restrict them to the AVX2 case since the simulated
+ CPUID we'll offer them on has AVX2 as a base. */
+ if (!have_avx2) {
+ have_f16c = False;
+ have_rdrand = False;
+ }
+
va = VexArchAMD64;
vai.endness = VexEndnessLE;
vai.hwcaps = (have_sse3 ? VEX_HWCAPS_AMD64_SSE3 : 0)
| (have_avx ? VEX_HWCAPS_AMD64_AVX : 0)
| (have_bmi ? VEX_HWCAPS_AMD64_BMI : 0)
| (have_avx2 ? VEX_HWCAPS_AMD64_AVX2 : 0)
- | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0);
+ | (have_rdtscp ? VEX_HWCAPS_AMD64_RDTSCP : 0)
+ | (have_f16c ? VEX_HWCAPS_AMD64_F16C : 0)
+ | (have_rdrand ? VEX_HWCAPS_AMD64_RDRAND : 0);
VG_(machine_get_cache_info)(&vai);
binop(Iop_V128HLtoV256, qV, shV));
}
+ case Iop_F32toF16x4: {
+ // First, PCast the input vector, retaining the 32x4 format.
+ IRAtom* pcasted = mkPCast32x4(mce, vatom2); // :: 32x4
+ // Now truncate each 32 bit lane to 16 bits. Since we already PCasted
+ // the input, we're not going to lose any information.
+ IRAtom* pcHI64
+ = assignNew('V', mce, Ity_I64, unop(Iop_V128HIto64, pcasted));//32x2
+ IRAtom* pcLO64
+ = assignNew('V', mce, Ity_I64, unop(Iop_V128to64, pcasted)); // 32x2
+ IRAtom* narrowed
+ = assignNew('V', mce, Ity_I64, binop(Iop_NarrowBin32to16x4,
+ pcHI64, pcLO64)); // 16x4
+ // Finally, roll in any badness from the rounding mode.
+ IRAtom* rmPCasted = mkPCastTo(mce, Ity_I64, vatom1);
+ return mkUifU64(mce, narrowed, rmPCasted);
+ }
+
+ case Iop_F32toF16x8: {
+ // Same scheme as for Iop_F32toF16x4.
+ IRAtom* pcasted = mkPCast32x8(mce, vatom2); // :: 32x8
+ IRAtom* pcHI128
+ = assignNew('V', mce, Ity_V128, unop(Iop_V256toV128_1,
+ pcasted)); // 32x4
+ IRAtom* pcLO128
+ = assignNew('V', mce, Ity_V128, unop(Iop_V256toV128_0,
+ pcasted)); // 32x4
+ IRAtom* narrowed
+ = assignNew('V', mce, Ity_V128, binop(Iop_NarrowBin32to16x8,
+ pcHI128, pcLO128)); // 16x8
+ // Finally, roll in any badness from the rounding mode.
+ IRAtom* rmPCasted = mkPCastTo(mce, Ity_V128, vatom1);
+ return mkUifUV128(mce, narrowed, rmPCasted);
+ }
+
default:
ppIROp(op);
VG_(tool_panic)("memcheck:expr2vbits_Binop");
case Iop_QNarrowUn64Sto32Sx2:
case Iop_QNarrowUn64Sto32Ux2:
case Iop_QNarrowUn64Uto32Ux2:
+ return vectorNarrowUnV128(mce, op, vatom);
+
+ // JRS FIXME 2019 Mar 17: per comments on F16toF32x4, this is probably not
+ // right.
case Iop_F32toF16x4_DEP:
return vectorNarrowUnV128(mce, op, vatom);
case Iop_Widen16Uto32x4:
case Iop_Widen32Sto64x2:
case Iop_Widen32Uto64x2:
+ return vectorWidenI64(mce, op, vatom);
+
case Iop_F16toF32x4:
+ // JRS 2019 Mar 17: this definitely isn't right, but it probably works
+ // OK by accident if -- as seems likely -- the F16 to F32 conversion
+ // preserves will generate an output 32 bits with at least one 1 bit
+ // set if there's one or more 1 bits set in the input 16 bits. More
+ // correct code for this is just below, but commented out, so as to
+ // avoid short-term backend failures on targets that can't do
+ // Iop_Interleave{LO,HI}16x4.
return vectorWidenI64(mce, op, vatom);
+ case Iop_F16toF32x8: {
+ // PCast the input at 16x8. This makes each lane hold either all
+ // zeroes or all ones.
+ IRAtom* pcasted = mkPCast16x8(mce, vatom); // :: I16x8
+ // Now double the width of each lane to 32 bits. Because the lanes are
+ // all zeroes or all ones, we can just copy the each lane twice into
+ // the result. Here's the low half:
+ IRAtom* widenedLO // :: I32x4
+ = assignNew('V', mce, Ity_V128, binop(Iop_InterleaveLO16x8,
+ pcasted, pcasted));
+ // And the high half:
+ IRAtom* widenedHI // :: I32x4
+ = assignNew('V', mce, Ity_V128, binop(Iop_InterleaveHI16x8,
+ pcasted, pcasted));
+ // Glue them back together:
+ return assignNew('V', mce, Ity_V256, binop(Iop_V128HLtoV256,
+ widenedHI, widenedLO));
+ }
+
+ // See comment just above, for Iop_F16toF32x4
+ //case Iop_F16toF32x4: {
+ // // Same scheme as F16toF32x4
+ // IRAtom* pcasted = mkPCast16x4(mce, vatom); // :: I16x4
+ // IRAtom* widenedLO // :: I32x2
+ // = assignNew('V', mce, Ity_I64, binop(Iop_InterleaveLO16x4,
+ // pcasted, pcasted));
+ // IRAtom* widenedHI // :: I32x4
+ // = assignNew('V', mce, Ity_I64, binop(Iop_InterleaveHI16x4,
+ // pcasted, pcasted));
+ // // Glue them back together:
+ // return assignNew('V', mce, Ity_V128, binop(Iop_64HLtoV128,
+ // widenedHI, widenedLO));
+ //}
+
case Iop_PwAddL32Ux2:
case Iop_PwAddL32Sx2:
return mkPCastTo(mce, Ity_I64,
{ DEFOP(Iop_Fixed32UToF32x4_RN, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Fixed32SToF32x4_RN, UNDEF_UNKNOWN), },
{ DEFOP(Iop_F32toF16x4_DEP, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_F32toF16x4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_F16toF32x4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_F64toF16x2_DEP, UNDEF_UNKNOWN), },
{ DEFOP(Iop_F16toF64x2, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Div32Fx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_I32StoF32x8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_F32toI32Sx8, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_F32toF16x8, UNDEF_UNKNOWN), },
+ { DEFOP(Iop_F16toF32x8, UNDEF_UNKNOWN) },
{ DEFOP(Iop_Sqrt32Fx8, UNDEF_UNKNOWN), },
{ DEFOP(Iop_Sqrt64Fx4, UNDEF_UNKNOWN), },
{ DEFOP(Iop_RSqrtEst32Fx8, UNDEF_UNKNOWN), },
clc.vgtest clc.stdout.exp clc.stderr.exp \
crc32.vgtest crc32.stdout.exp crc32.stderr.exp \
cmpxchg.vgtest cmpxchg.stdout.exp cmpxchg.stderr.exp \
+ f16c.vgtest f16c.stderr.exp f16c.stdout.exp \
faultstatus.disabled faultstatus.stderr.exp \
fb_test_amd64.vgtest \
fb_test_amd64.stderr.exp fb_test_amd64.stdout.exp \
pcmpxstrx64w.stderr.exp pcmpxstrx64w.stdout.exp \
pcmpxstrx64w.vgtest \
rcl-amd64.vgtest rcl-amd64.stdout.exp rcl-amd64.stderr.exp \
+ rdrand.vgtest rdrand.stdout.exp rdrand.stderr.exp \
redundantRexW.vgtest redundantRexW.stdout.exp \
redundantRexW.stderr.exp \
smc1.stderr.exp smc1.stdout.exp smc1.vgtest \
if BUILD_MPX_TESTS
check_PROGRAMS += mpx
endif
+if BUILD_F16C_TESTS
+ check_PROGRAMS += f16c
+endif
+if BUILD_RDRAND_TESTS
+ check_PROGRAMS += rdrand
+endif
# DDD: these need to be made to work on Darwin like the x86/ ones were.
--- /dev/null
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "tests/malloc.h"
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+typedef unsigned long int UWord;
+typedef unsigned long long int ULong;
+
+#define IS_32_ALIGNED(_ptr) (0 == (0x1F & (UWord)(_ptr)))
+
+typedef union { UChar u8[32]; UInt u32[8]; } YMM;
+
+typedef struct { YMM a1; YMM a2; YMM a3; YMM a4; ULong u64; } Block;
+
+void showYMM ( YMM* vec )
+{
+ int i;
+ assert(IS_32_ALIGNED(vec));
+ for (i = 31; i >= 0; i--) {
+ printf("%02x", (UInt)vec->u8[i]);
+ if (i > 0 && 0 == ((i+0) & 7)) printf(".");
+ }
+}
+
+void showBlock ( char* msg, Block* block )
+{
+ printf(" %s\n", msg);
+ printf(" "); showYMM(&block->a1); printf("\n");
+ printf(" "); showYMM(&block->a2); printf("\n");
+ printf(" "); showYMM(&block->a3); printf("\n");
+ printf(" "); showYMM(&block->a4); printf("\n");
+ printf(" %016llx\n", block->u64);
+}
+
+UChar randUChar ( void )
+{
+ static UInt seed = 80021;
+ seed = 1103515245 * seed + 12345;
+ return (seed >> 17) & 0xFF;
+}
+
+void randBlock ( Block* b )
+{
+ int i;
+ UChar* p = (UChar*)b;
+ for (i = 0; i < sizeof(Block); i++)
+ p[i] = randUChar();
+}
+
+
+/* Generate a function test_NAME, that tests the given insn, in both
+ its mem and reg forms. The reg form of the insn may mention, as
+ operands only %ymm6, %ymm7, %ymm8, %ymm9 and %r14. The mem form of
+ the insn may mention as operands only (%rax), %ymm7, %ymm8, %ymm9
+ and %r14. It's OK for the insn to clobber ymm0, as this is needed
+ for testing PCMPxSTRx, and ymm6, as this is needed for testing
+ MOVMASK variants. */
+
+#define GEN_test_RandM(_name, _reg_form, _mem_form) \
+ \
+ __attribute__ ((noinline)) static void test_##_name ( void ) \
+ { \
+ Block* b = memalign32(sizeof(Block)); \
+ randBlock(b); \
+ printf("%s(reg)\n", #_name); \
+ showBlock("before", b); \
+ __asm__ __volatile__( \
+ "vmovdqa 0(%0),%%ymm7" "\n\t" \
+ "vmovdqa 32(%0),%%ymm8" "\n\t" \
+ "vmovdqa 64(%0),%%ymm6" "\n\t" \
+ "vmovdqa 96(%0),%%ymm9" "\n\t" \
+ "movq 128(%0),%%r14" "\n\t" \
+ _reg_form "\n\t" \
+ "vmovdqa %%ymm7, 0(%0)" "\n\t" \
+ "vmovdqa %%ymm8, 32(%0)" "\n\t" \
+ "vmovdqa %%ymm6, 64(%0)" "\n\t" \
+ "vmovdqa %%ymm9, 96(%0)" "\n\t" \
+ "movq %%r14, 128(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"xmm0","xmm7","xmm8","xmm6","xmm9","r14","memory","cc" \
+ ); \
+ showBlock("after", b); \
+ randBlock(b); \
+ printf("%s(mem)\n", #_name); \
+ showBlock("before", b); \
+ __asm__ __volatile__( \
+ "leaq 0(%0),%%rax" "\n\t" \
+ "vmovdqa 32(%0),%%ymm8" "\n\t" \
+ "vmovdqa 64(%0),%%ymm7" "\n\t" \
+ "vmovdqa 96(%0),%%ymm9" "\n\t" \
+ "movq 128(%0),%%r14" "\n\t" \
+ _mem_form "\n\t" \
+ "vmovdqa %%ymm8, 32(%0)" "\n\t" \
+ "vmovdqa %%ymm7, 64(%0)" "\n\t" \
+ "vmovdqa %%ymm9, 96(%0)" "\n\t" \
+ "movq %%r14, 128(%0)" "\n\t" \
+ : /*OUT*/ \
+ : /*IN*/"r"(b) \
+ : /*TRASH*/"xmm6", \
+ "xmm0","xmm8","xmm7","xmm9","r14","rax","memory","cc" \
+ ); \
+ showBlock("after", b); \
+ printf("\n"); \
+ free(b); \
+ }
+
+#define GEN_test_Ronly(_name, _reg_form) \
+ GEN_test_RandM(_name, _reg_form, "")
+#define GEN_test_Monly(_name, _mem_form) \
+ GEN_test_RandM(_name, "", _mem_form)
+
+GEN_test_RandM(VCVTPH2PS_128,
+ "vcvtph2ps %%xmm6, %%xmm8",
+ "vcvtph2ps (%%rax), %%xmm8");
+GEN_test_RandM(VCVTPH2PS_256,
+ "vcvtph2ps %%xmm6, %%ymm8",
+ "vcvtph2ps (%%rax), %%ymm8");
+
+GEN_test_RandM(VCVTPS2PH_128_0,
+ "vcvtps2ph $0, %%xmm8, %%xmm6",
+ "vcvtps2ph $0, %%xmm8, (%%rax)");
+GEN_test_RandM(VCVTPS2PH_256_0,
+ "vcvtps2ph $0, %%ymm8, %%xmm6",
+ "vcvtps2ph $0, %%ymm8, (%%rax)");
+
+GEN_test_RandM(VCVTPS2PH_128_1,
+ "vcvtps2ph $1, %%xmm8, %%xmm6",
+ "vcvtps2ph $1, %%xmm8, (%%rax)");
+GEN_test_RandM(VCVTPS2PH_256_1,
+ "vcvtps2ph $1, %%ymm8, %%xmm6",
+ "vcvtps2ph $1, %%ymm8, (%%rax)");
+
+GEN_test_RandM(VCVTPS2PH_128_2,
+ "vcvtps2ph $2, %%xmm8, %%xmm6",
+ "vcvtps2ph $2, %%xmm8, (%%rax)");
+GEN_test_RandM(VCVTPS2PH_256_2,
+ "vcvtps2ph $2, %%ymm8, %%xmm6",
+ "vcvtps2ph $2, %%ymm8, (%%rax)");
+
+GEN_test_RandM(VCVTPS2PH_128_3,
+ "vcvtps2ph $3, %%xmm8, %%xmm6",
+ "vcvtps2ph $3, %%xmm8, (%%rax)");
+GEN_test_RandM(VCVTPS2PH_256_3,
+ "vcvtps2ph $3, %%ymm8, %%xmm6",
+ "vcvtps2ph $3, %%ymm8, (%%rax)");
+
+GEN_test_RandM(VCVTPS2PH_128_4,
+ "vcvtps2ph $4, %%xmm8, %%xmm6",
+ "vcvtps2ph $4, %%xmm8, (%%rax)");
+GEN_test_RandM(VCVTPS2PH_256_4,
+ "vcvtps2ph $4, %%ymm8, %%xmm6",
+ "vcvtps2ph $4, %%ymm8, (%%rax)");
+
+/* Comment duplicated above, for convenient reference:
+ Allowed operands in test insns:
+ Reg form: %ymm6, %ymm7, %ymm8, %ymm9 and %r14.
+ Mem form: (%rax), %ymm7, %ymm8, %ymm9 and %r14.
+ Imm8 etc fields are also allowed, where they make sense.
+ Both forms may use ymm0 as scratch. Mem form may also use
+ ymm6 as scratch.
+*/
+
+#define N_DEFAULT_ITERS 3
+
+// Do the specified test some number of times
+#define DO_N(_iters, _testfn) \
+ do { int i; for (i = 0; i < (_iters); i++) { test_##_testfn(); } } while (0)
+
+// Do the specified test the default number of times
+#define DO_D(_testfn) DO_N(N_DEFAULT_ITERS, _testfn)
+
+
+int main ( void )
+{
+ DO_D( VCVTPH2PS_128 );
+ DO_D( VCVTPH2PS_256 );
+
+ DO_D( VCVTPS2PH_128_0 );
+ DO_D( VCVTPS2PH_256_0 );
+
+ DO_D( VCVTPS2PH_128_1 );
+ DO_D( VCVTPS2PH_256_1 );
+
+ DO_D( VCVTPS2PH_128_2 );
+ DO_D( VCVTPS2PH_256_2 );
+
+ DO_D( VCVTPS2PH_128_3 );
+ DO_D( VCVTPS2PH_256_3 );
+
+ DO_D( VCVTPS2PH_128_4 );
+ DO_D( VCVTPS2PH_256_4 );
+
+ return 0;
+}
--- /dev/null
+VCVTPH2PS_128(reg)
+ before
+ 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700
+ b6d2fb5aa7bc5127.fe9915e556a044b2.60b160857d45c484.47b8d8c0eeef1e50
+ 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+ cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5
+ 56b01a12b0ca1583
+ after
+ 7d6528c5fa956a0d.69c3e9a6af27d13b.5175e39d19c9ca1e.98f24a4984175700
+ 0000000000000000.0000000000000000.3f322000b8308000.c37980003da70000
+ 065d77195d623e6b.842adc6450659e17.19a348215c3a67fd.399182c2dbcc2d38
+ cb509970b8136c85.d740b80eb7839b97.d89998df5035ed36.4a4bc43968bc40e5
+ 56b01a12b0ca1583
+VCVTPH2PS_128(mem)
+ before
+ 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db
+ cfaff39be272ef40.20a1bb92cbc97fe8.542da4983df76c96.d8bc5c6dee699597
+ f4e06e2205236eb7.6897b536bbe4da8a.369dab4f9465b86e.d182c916cebc2e17
+ 84ededbc53239dcf.95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06
+ 81f2a547be8d1811
+ after
+ 398e0039cf03663d.5ff85bc9535c191f.d3a727d1a705f65d.f9dd4a29f8c093db
+ 0000000000000000.0000000000000000.c73ba00041452000.c7180000ba7b6000
+ f4e06e2205236eb7.6897b536bbe4da8a.369dab4f9465b86e.d182c916cebc2e17
+ 84ededbc53239dcf.95264321bf3b68b2.55c2b9e2c95c9810.407b8d9035449b06
+ 81f2a547be8d1811
+
+VCVTPH2PS_128(reg)
+ before
+ f0350ca70523e0e4.5ba1ec54e87d39b3.019963bf7459630b.8d69483df7e8c6a9
+ e98ebd1ca893312a.54cae7d5e13dfe91.0a3e0f7c75cb0842.b95ed64d3b13ff64
+ c84ab71340684590.4d325b2d5a70a792.0a5f45c55f1c9202.b76ddefcb0ebfe6e
+ e9b5f3f66b2e58c1.21a6c3476d21f1e5.5f490104ced83ff8.6262dd37727c80f3
+ 96084deb9ed0411e
+ after
+ f0350ca70523e0e4.5ba1ec54e87d39b3.019963bf7459630b.8d69483df7e8c6a9
+ 0000000000000000.0000000000000000.beeda000c3df8000.be1d6000ffcdc000
+ c84ab71340684590.4d325b2d5a70a792.0a5f45c55f1c9202.b76ddefcb0ebfe6e
+ e9b5f3f66b2e58c1.21a6c3476d21f1e5.5f490104ced83ff8.6262dd37727c80f3
+ 96084deb9ed0411e
+VCVTPH2PS_128(mem)
+ before
+ 2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4.63483da65c8c49d0
+ 089b756aa3f77018.61c82534e9bf6f37.c9e25f72d82e582b.73a8f718a8c3ec35
+ ff1f240eb3e1553f.6f07136773a2ead3.56428c5a66a2ec77.ecb42ac54b0966d4
+ ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4.28bad218e4ebf159
+ 8404eb7f0cf4ca6f
+ after
+ 2e2dac0350f6fd1c.a81b6e33c572a86a.acf29b0f395c98b4.63483da65c8c49d0
+ 0000000000000000.0000000000000000.446900003fb4c000.43918000413a0000
+ ff1f240eb3e1553f.6f07136773a2ead3.56428c5a66a2ec77.ecb42ac54b0966d4
+ ee8536da9dbf68bc.3026343700a654eb.2ddd9db4ffc411c4.28bad218e4ebf159
+ 8404eb7f0cf4ca6f
+
+VCVTPH2PS_128(reg)
+ before
+ 5cdf726562b02dc2.b39925ba7d9d67bc.ff6f850f2c57ea2a.2c810e6dc1a1833d
+ 0c9761367fac55ff.28276f9a6e880c6b.372f015d9242e83d.2ef85b6fc544fd0f
+ f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ 65ce6d498492e7e7.96df010bf4b23b84.57436a097df30b8d.aa927a03090dfc6d
+ dc4c446c804bf950
+ after
+ 5cdf726562b02dc2.b39925ba7d9d67bc.ff6f850f2c57ea2a.2c810e6dc1a1833d
+ 0000000000000000.0000000000000000.39c1e00037d40000.3d3740003f8cc000
+ f078b65e01737fd2.2bfa8f668c8b14f4.36b2a38dcef18acf.0e0f01a829ba3c66
+ 65ce6d498492e7e7.96df010bf4b23b84.57436a097df30b8d.aa927a03090dfc6d
+ dc4c446c804bf950
+VCVTPH2PS_128(mem)
+ before
+ 810bdacfab80ee3d.c5e48064a393c8e9.47a34273c10a3c47.f5304f3e3ad1a923
+ 769ab818a5b7985e.6d08ed19fa045f84.1810cd8c109ed568.6ec34f98a2199d3c
+ 95c45b338afcb3df.b984aed62671e865.e6f21d40fc7bc013.1c4a678450562685
+ bc563e0c775bfaed.05a5c205c3659f38.8e17b17da2acb976.5d0f926ce1157eaa
+ 8b5fccbef0e1e256
+ after
+ 810bdacfab80ee3d.c5e48064a393c8e9.47a34273c10a3c47.f5304f3e3ad1a923
+ 0000000000000000.0000000000000000.c6a6000041e7c000.3f5a2000bd246000
+ 95c45b338afcb3df.b984aed62671e865.e6f21d40fc7bc013.1c4a678450562685
+ bc563e0c775bfaed.05a5c205c3659f38.8e17b17da2acb976.5d0f926ce1157eaa
+ 8b5fccbef0e1e256
+
+VCVTPH2PS_256(reg)
+ before
+ 048612e51a468e36.c51cdd8f87e12ab4.acb722146c6cbfa9.ea4a022e1d3d7dbb
+ 22cf5e4cfad1bdf5.8de2b4a9d799ff5f.0c05cb6ebd128663.d7568e3e8a3ac80e
+ 4288ae612c0dad40.f0733f448390351b.80ddba7e53e42d12.3208cf9b04b0569c
+ c1fbfd8f4d8698c2.cb9dfb4ea5d18713.6489eab2c96df363.d52c4330a7aae391
+ 9d8e66ea90352a18
+ after
+ 048612e51a468e36.c51cdd8f87e12ab4.acb722146c6cbfa9.ea4a022e1d3d7dbb
+ b75d0000bf4fc000.427c80003da24000.3e410000c1f36000.3896000042d38000
+ 4288ae612c0dad40.f0733f448390351b.80ddba7e53e42d12.3208cf9b04b0569c
+ c1fbfd8f4d8698c2.cb9dfb4ea5d18713.6489eab2c96df363.d52c4330a7aae391
+ 9d8e66ea90352a18
+VCVTPH2PS_256(mem)
+ before
+ 66fab2b3db5ce85e.f9754842f9c9ba28.f82a63b15c68b274.14575775bc3a1202
+ 0c3ca578a32bd88e.474289e7cb61501e.54e7f35bc162726a.ec91fe34c7d6c79a
+ 6b1fba2604afb8d5.08aebee85fda964f.bba02737f3c98220.4784d95987cd4ed8
+ 5f706da71bf2425f.9605e2b252c1c868.09217c310baca0c3.837be65197abe268
+ fbc4208894fdc0f5
+ after
+ 66fab2b3db5ce85e.f9754842f9c9ba28.f82a63b15c68b274.14575775bc3a1202
+ c705400044762000.438d0000be4e8000.3a8ae00042eea000.bf8740003a404000
+ 6b1fba2604afb8d5.08aebee85fda964f.bba02737f3c98220.4784d95987cd4ed8
+ 5f706da71bf2425f.9605e2b252c1c868.09217c310baca0c3.837be65197abe268
+ fbc4208894fdc0f5
+
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+ e80f3f1bf2b5b476
+VCVTPS2PH_256_4(mem)
+ before
+ 9444b197ac07cce3.ec6d05a4b6a1a4cd.9e88325743eb11d5.19fee7710650f247
+ 50072abaf61c5a46.eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92
+ f727286eebfe18c9.4fd84b29b99a6b2d.cd4345d71d165b24.ef23560adb3157cc
+ 656f27a1a7bbc398.727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2
+ 0d4312973a16fac0
+ after
+ 9444b197ac07cce3.ec6d05a4b6a1a4cd.7c00fc00fc00fc00.7c00000000007c00
+ 50072abaf61c5a46.eb961e83edc02ffa.57cb79e901fcadd7.0937b3956de6fb92
+ f727286eebfe18c9.4fd84b29b99a6b2d.cd4345d71d165b24.ef23560adb3157cc
+ 656f27a1a7bbc398.727e8a02b5bb9511.dbbd140db245d8e8.270ecc3cebbd43a2
+ 0d4312973a16fac0
+
+VCVTPS2PH_256_4(reg)
+ before
+ fd0f238763c9b9d1.76aaa13e475e17e0.b2d6d57a7db0e953.5f056177dd93e04f
+ 52bffb790361bc82.06a61431e6f4cfcd.692a2afdae04a39e.34e7a802b90e2f84
+ 6a9d96d7b56b3f7e.f02dfb66a188a88b.f4c785f8e443fea0.362f659862c280b3
+ a0f5f10f15717d72.120cd2c993275e44.b0f9e0d5b9fa3702.41a91527f6b99009
+ 302032998e011bb2
+ after
+ fd0f238763c9b9d1.76aaa13e475e17e0.b2d6d57a7db0e953.5f056177dd93e04f
+ 52bffb790361bc82.06a61431e6f4cfcd.692a2afdae04a39e.34e7a802b90e2f84
+ 0000000000000000.0000000000000000.7c0000000000fc00.7c00800000078871
+ a0f5f10f15717d72.120cd2c993275e44.b0f9e0d5b9fa3702.41a91527f6b99009
+ 302032998e011bb2
+VCVTPS2PH_256_4(mem)
+ before
+ e1613adc48a6dcd9.5015078bc002b309.470f1546d9dbad27.f70c3901ccb48a72
+ 2f38a8db40b290ab.d648d4b952a71df1.6a0141c98eb2505e.264b8be9b6fd329c
+ f571f9829134f354.8dd9540466eef7d3.59b0d13fcfb80416.9a04d2f816626c2c
+ 11d8a7bd5735c0ff.d31583d898627c5e.efe64192b7f7857a.ad810a9a856e74cd
+ bc0f303ba1ad862b
+ after
+ e1613adc48a6dcd9.5015078bc002b309.00004595fc007c00.7c0080000000807f
+ 2f38a8db40b290ab.d648d4b952a71df1.6a0141c98eb2505e.264b8be9b6fd329c
+ f571f9829134f354.8dd9540466eef7d3.59b0d13fcfb80416.9a04d2f816626c2c
+ 11d8a7bd5735c0ff.d31583d898627c5e.efe64192b7f7857a.ad810a9a856e74cd
+ bc0f303ba1ad862b
+
--- /dev/null
+prog: f16c
+prereq: test -x f16c && ../../../tests/x86_amd64_features amd64-f16c
+vgopts: -q
--- /dev/null
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <assert.h>
+#include "tests/malloc.h"
+
+typedef unsigned char UChar;
+typedef unsigned int UInt;
+typedef unsigned long int UWord;
+typedef unsigned long long int ULong;
+
+// What can we actually test here? The instructions take no input and
+// produce output which is by definition totally random. So apart from
+// not simply failing insn decode, there's nothing much to test.
+
+// Get 10 values of each size, and check that they are not all the same
+// (otherwise something's obviously wrong). Now, statistically, it's
+// highly unlikely that they are all the same. For 10 16 bit ints, the
+// probability of them being all the same is (I'd guess) (2^-16) ^ (10-1),
+// that is, 2^-144.
+
+ULong do_rdrand64 ( void )
+{
+ while (1) {
+ ULong res = 0;
+ ULong cflag = 0;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11 ; "
+ "movq $0, %%r12 ; "
+ "rdrand %%r11 ; "
+ "setc %%r12b ; "
+ "movq %%r11, %0 ; "
+ "movq %%r12, %1"
+ : "=r"(res), "=r"(cflag) : : "r11", "r12"
+ );
+ if (cflag == 1)
+ return res;
+ }
+ /*NOTREACHED*/
+}
+
+ULong do_rdrand32 ( void )
+{
+ while (1) {
+ ULong res = 0;
+ ULong cflag = 0;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11 ; "
+ "movq $0, %%r12 ; "
+ "rdrand %%r11d ; "
+ "setc %%r12b ; "
+ "movq %%r11, %0 ; "
+ "movq %%r12, %1"
+ : "=r"(res), "=r"(cflag) : : "r11", "r12"
+ );
+ if (cflag == 1)
+ return res;
+ }
+ /*NOTREACHED*/
+}
+
+ULong do_rdrand16 ( void )
+{
+ while (1) {
+ ULong res = 0;
+ ULong cflag = 0;
+ __asm__ __volatile__(
+ "movabsq $0x5555555555555555, %%r11 ; "
+ "movq $0, %%r12 ; "
+ "rdrand %%r11w ; "
+ "setc %%r12b ; "
+ "movq %%r11, %0 ; "
+ "movq %%r12, %1"
+ : "=r"(res), "=r"(cflag) : : "r11", "r12"
+ );
+ if (cflag == 1)
+ return res;
+ }
+ /*NOTREACHED*/
+}
+
+void do_test ( ULong(*fn)(void),
+ ULong mask
+ /* with 1s indicating the random bits in the result */ )
+{
+ ULong arr[10];
+ for (UInt i = 0; i < 10; i++) {
+ arr[i] = fn();
+ }
+
+ // They really should all be different (to an extremely high probabilty.
+ // See comment above.
+ int allSame = 1/*true*/; // really, a Bool
+ for (UInt i = 1; i < 10; i++) {
+ if (arr[i] != arr[0]) {
+ allSame = 0/*false*/;
+ break;
+ }
+ }
+ assert(!allSame);
+
+ // The 0/32/48 leading bits of the result should have a particular value,
+ // depending on the insn. So print them, with the random part masked out.
+ for (UInt i = 0; i < 10; i++) {
+ printf("0x%016llx\n", arr[i] & ~mask);
+ }
+ printf("\n");
+}
+
+int main ( void )
+{
+ do_test( do_rdrand64, 0xFFFFFFFFFFFFFFFFULL );
+ do_test( do_rdrand32, 0x00000000FFFFFFFFULL );
+ do_test( do_rdrand16, 0x000000000000FFFFULL );
+ return 0;
+}
--- /dev/null
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+0x0000000000000000
+
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+0x5555555555550000
+
--- /dev/null
+prog: rdrand
+prereq: test -x rdrand && ../../../tests/x86_amd64_features amd64-rdrand
+vgopts: -q
// This file determines x86/AMD64 features a processor supports.
//
// We return:
-// - 0 if the machine matches the asked-for feature.
-// - 1 if the machine does not.
+// - 0 if the machine has the asked-for feature.
+// - 1 if the machine doesn't have the asked-for feature.
// - 2 if the asked-for feature isn't recognised (this will be the case for
// any feature if run on a non-x86/AMD64 machine).
// - 3 if there was a usage error (it also prints an error message).
level = 0x80000001;
cmask = 1 << 16;
require_amd = True;
+ } else if (strcmp (cpu, "amd64-f16c" ) == 0) {
+ level = 1;
+ cmask = 1 << 29;
+ } else if (strcmp (cpu, "amd64-rdrand" ) == 0) {
+ level = 1;
+ cmask = 1 << 30;
#endif
} else {
return UNRECOGNISED_FEATURE;
projects / thirdparty / valgrind.git / commitdiff
