clk: hi3798cv200: correct IR clock parent

The IR clock is sourced from '24m' rather than '100m'.  Correct it.

Signed-off-by: Younian Wang <wangyounian@hisilicon.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c
index c586c79f46238c18b09f596a221576172279284e..d7d1ba0153ecf2d763687bb01c2e78ac29bf668d 100644 (file)
--- a/drivers/clk/hisilicon/crg-hi3798cv200.c
+++ b/drivers/clk/hisilicon/crg-hi3798cv200.c
@@ -244,7 +244,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
 #define HI3798CV200_SYSCTRL_NR_CLKS 16
 
 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
-       { HISTB_IR_CLK, "clk_ir", "100m",
+       { HISTB_IR_CLK, "clk_ir", "24m",
                CLK_SET_RATE_PARENT, 0x48, 4, 0, },
        { HISTB_TIMER01_CLK, "clk_timer01", "24m",
                CLK_SET_RATE_PARENT, 0x48, 6, 0, },