soc: renesas: rcar-rst: Keep RESBAR2S in default state

Unlike Gen2, Gen4 has bit 15 of WDTRSTCR register also used. Keep it in
the default state for the V3U firmware workaround.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251017114234.2968-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/soc/renesas/rcar-rst.c b/drivers/soc/renesas/rcar-rst.c
index 7ba02f3a4a4fbb9fc41f7c08d5a438de7f16569e..0541990901fcbd37946d08b0d2e9cb9593e52853 100644 (file)
--- a/drivers/soc/renesas/rcar-rst.c
+++ b/drivers/soc/renesas/rcar-rst.c
@@ -12,6 +12,7 @@
 
 #define WDTRSTCR_RESET         0xA55A0002
 #define WDTRSTCR               0x0054
+#define GEN4_WDTRSTCR_RESET    0xA55A8002
 #define GEN4_WDTRSTCR          0x0010
 
 #define CR7BAR                 0x0070
@@ -30,7 +31,7 @@ static int rcar_rst_enable_wdt_reset(void __iomem *base)
 
 static int rcar_rst_v3u_enable_wdt_reset(void __iomem *base)
 {
-       iowrite32(WDTRSTCR_RESET, base + GEN4_WDTRSTCR);
+       iowrite32(GEN4_WDTRSTCR_RESET, base + GEN4_WDTRSTCR);
        return 0;
 }